A new memory-based architecture for real-time image convolution with variable kernels is proposed. The architecture exploits the highest possible bandwidth inherent in memory and achieves the fine-grain parallelism of computations inside the memory. Unlike existing approaches, the architecture ensures convolution with very large kernels under the real time constraints of video applications. It ...

Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based arc...

The design and architecture of a memory test synthesis framework for automatic generation, insertion and veriication of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The exibility and eeciency of the framework are demonstrated by showing that memory BIST units with diierent architecture and characteristics could be...

　Introduction: Previous studies have suggested that the cerebellum is a primary site of motor learning. The cerebellar cortex has a particular glial architecture with large astroglial cells. In addition, more recent works have revealed that astrocytes play a more active role in neuronal activity. The aim of this study was to evaluate the number of astrocytes in the molecular layer of rat's cere...

Memory represents a major bottleneck in modern embedded systems in terms of cost, power and performance. Traditionally, memory organizations for programmable systems assume a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. H...

An architecture for experimenting with different algorithms in numeric/symbolic computing, concurrent programming paradigms, and interconnection networks is proposed. The architecture comprises a large collection of processors organized in groups called levels. Each level has interconnection networks to communicate with memory units in the level and also a global memory called system memory. Ea...

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of an effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture that performs the depth test twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste due to fetching unnecessary o...

We propose a new architecture for shared memory multiprocessors, the crosspoint cache architecture. This architecture consists of a crossbar interconnection network with a cache memory at each crosspoint switch. It assures cache coherence in hardware while avoiding the performance bottlenecks associated with previous hardware cache coherence solutions. We show this architecture is feasible for ...

To improve memory bandwidth and power consumption in video applications, a new memory-interface architecture is proposed. The architecture adopts an array address-translation technique to utilize the fact that video-processing algorithms have regular memory-access patterns. Since the translation can minimize the number of overhead cycles needed for row-activations in synchronous DRAM (SDRAM), w...

There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to the indirection introduced by the accesses to directory information, usually stored in main memory. This work presents a lightweight directory architecture aimed at facing these two important problems. Our proposal ta...