According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing system on chips (SoCs) content in the future, approaching 90% in in some cases. Therefore, the memory yield and quality will have a dramatic impact on the overall SoC cost and outgoing product quality. Meeting a high memory yield and quality requires understanding mem...

As the capacity and density of embedded memories have rapidly increased, the probability of memory faults will increase. That results in yield drops and quality degradation.Yield improvement of embedded memories have become very important.Yield refers to the percentage of good die on the wafer. For embedded memories Built-In-Redundancy-Analysis (BIRA)is used to achieve optimal repair rate and y...

Fast time-to-market for mixed-signal ASICs with embedded non-volatile memory (NVM) requires robust IP blocks of different array sizes. This paper describes array topology, design architecture and digital wrapper trade-offs that must be considered in designing a scalable NVM. Specific time generator, sense amplifier and array topology are displayed as well as a BIST specific approach. Finally HI...

In this paper, we show a method to locate a single stuckat fault of a random access memory (RAM). From the fail-bitmaps of the RAM, we obtain their Walsh spectrum. For a single stuck-at fault, we show that the fault can be identified and located by using only the 0-th and 1-st coefficients of the spectrum. We also show a circuit to compute these coefficients. The computation time is O(2n), wher...

This project presents a scheme for detecting and diagnosing faults that are commonly occurred random access memory and Read only memory. The build in self test technique is used to identify permanent failures in embedded memories. The target of the project is fault detection and diagnosis in ROM and RAM such as single cell faults, row and column wise faults using Build in self test. In all the ...

Built-in Self-Test (BIST) approaches for Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) must be capable of fully testing the resources in the device. A summary of current techniques is presented in this paper that covers the three main components of modern FPGAs: logic blocks, interconnects and embedded FPGA cores. Overhead requirements, coverage capability, tra...

Umbra is an efficient and scalable memory shadowing tool built on top of DynamoRIO, which is a state-ofthe-art runtime code manipulation system. Using the APIs provided by DynamoRIO, Umbra inserts code into the applications runtime instruction stream to perform memory address translation from application memory to shadow memory. Umbra also provides a simple interface that enables developers to ...

-Ihis paper presents a testable design of dynamic randomaccess memory (DRAM) architecture which allows one to access multiple cells in a word l i e simultaneously. The technique utilizes the two-dimensional (2D) organization of the DRAM and the resulting speedup of the conventional algorithms is considerable. This paper specifically investigates the failure mechanisms in the three-dimensional (...

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM thirdgeneration embedded dynamic random-access memory (DRAM) for the IBM Blue Logic 0.11m application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamenta...

A highly dependable embedded fault-tolerant memory architecture for high performance massively parallel computing applications and its dependability assurance techniques are proposed and discussed in this paper. The proposed fault tolerant memory provides two distinctive repair mechanisms: the permanent laser redundancy reconfiguration during the wafer probe stage in the factory to enhance its ...