Current cache coherence protocols limit the scalability of chip multiprocessor (CMP) architectures. The expected increase of the number of cores in next generation CMPs call for an evolution of the memory subsystem. One solution is to introduce a local memory side to the cache hierarchy, forming a hybrid memory model. On the one hand, local memories are more power-efficient than caches and they...

As Internet is becoming popular to everyone recently, demands for higher-quality services such as VOD and home networking have been increasing. Especially, home networking system can interconnect and control home appliances which use different protocols via Internet. This means that a common protocol to communicate with each other and a new system architecture to implement the common protocol a...

We use the Abstract State Machine methodology to give formal operational semantics for the Location Consistency memory model and cache protocol. With these formal models, we prove that the cache protocol satisfies the memory model, but in a way that is strictly stronger than necessary, disallowing certain behavior allowed by

Software-implementations of shared memory are still far behind the performance of hardwarebased shared memory implementations and are not viable options for most fine-grain sharedmemory applications. The major source for their inefficiency comes from the cost of interruptbased asynchronous protocol processing, not from the actual network latency. As the raw hardware latency of inter-node commun...

Transactional memory is an alternative programming model for managing contention in accessing shared in-memory data objects. Distributed transactional memory promises to alleviate difficulties with lock-based (distributed) synchronization and object performance bottlenecks in distributed systems. The design of the cache-coherence protocol is critical to the performance of distributed transactio...

A DSM (Distributed-Shared Memory) cluster is an attractive parallel computing platform for scienti c research as it provides programming advantages within a scalable and cost-e ective hardware solution. This bene t derives from the fact that a DSM system provides a shared-memory abstraction on top of a distributed-memory machine by caching data replicas locally. In this respect, a coherence pro...

We propose a memory efficient self-stabilizing protocol building distance-k independent dominating sets. A distance-k independent dominating set is a distance-k independent set and a distance-k dominating set. Our algorithm, named SID, is silent; it converges under the unfair distributed scheduler (the weakest scheduling assumption). The protocol SID is memory efficient : it requires only log(2...

ÐScalable distributed shared-memory architectures rely on coherence controllers on each processing node to synthesize cache-coherent shared memory across the entire machine. The coherence controllers execute coherence protocol handlers that may be hardwired in custom hardware or programmed in a protocol processor within each coherence controller. Although custom hardware runs faster, a protocol...

In this thesis, GEMS (a Generic Environment for Multiprocessor Simulations) is presented. GEMS is a simulation environment written in the Superlog language, which simulates a configurable shared-memory multiprocessor system. Simulation focuses on the memory hierarchy and the system interconnect. Part of GEMS is a directory-based cache coherence protocol. This protocol is an adaptation of the bu...

The Internet's core is TCP/IP, which stands for Transmission Control Protocol/Internet Protocol. It connects network devices on the internet via communication protocols. Python has several TCP/IP packages due to its popularity and flexibility. This paper describes most popular libraries protocol implementation, including socket, asyncio, Twisted, Scapy. To help developers choose a library, we c...