the mixed-signal circuits with both analog and digital blocks on a single chip have wide applications in communication and rf circuits. integrating these two blocks can cause serious problems especially in applications requiring fast digital circuits and high performance analog blocks. fast switching in digital blocks generates a noise which can be introduced to analog circuits by the common su...

A multiple pass A/D conversion technique is proposed for mixed-signal test applications. Only a single on-chip comparator and sample-and-hold circuit is required to digitize repetitive analog waveforms. Simulations show 10 bits of amplitude resolution at 300 MHz for a bipolar comparator design (0.8 μm BiCMOS process), and 10 bits of amplitude resolution at 667 MHz for a CMOS comparator design (...

In this paper we propose successive interference cancellers (IC) for variable data rate directsequence code division multiple access (DS/CDMA) systems. The performance under Rayleigh fading is analysed for single modulation systems and different systems for handling multiple data rates. One alternative for handling multi-rate systems is to use mixed modulation, which imply that each user choose...

In this paper we analyse a successive IC scheme for higher modulation in DS/CDMA systems. The performance under Rayleigh fading is analysed for single modulation systems and systems employing either of two different methods, mixed modulation or parallel channels, for handling multiple data rates. We show that the successive IC scheme for higher modulation together with mixed modulation or paral...

|A methodology for structural fault-model based test generation for embedded analog macros in mixed-signal ICs is presented. From the IC-level, parameters reeecting the testability limitations faced by an analog macro under test (MUT) due to surrounding macros are extracted. This method is also suited for quantifying testability reduction and identiication of eecient test insertion points. The ...

A method of performing analog/mixed signal test will be described based on the assumption that: 1. All failure modes do not have to be defined. 2. The majority of failures are described by catastrophic faults [1-3]. Working forward from these assumptions, a comprehensive method will be presented that results in identifying a test suite that can serve either as a product acceptance test or a fie...

Supply Current Testing (IDDQ) has become an important defect oriented test strategy for digital IC products. The technique takes advantage of the low quiescent supply current drawn by static CMOS circuits relative to the current consumption during state changes. However, in analogue and mixed signal IC’s this condition can rarely be observed, as in most circuits, steady state currents depend on...

A mixed-signal IC controller is described for singlephase PFC applications. The single-chip controller block diagram is described, and the fundamental analog and digital operating blocks are developed in detail. Implementation options for each block are given, with experimental results from a 1.2μ CMOS test chip included. The controller blocks are derived for boost and buck/boost type converter...

An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement...

Voltage nonlinearity is a crucial performance parameter of MIM capacitors for RF, analog and mixed signal IC applications. In present work, the fabrication and characterization of anodic high-k MIM capacitors are reported in detail and modeling of nonlinearity coefficient of capacitance is developed using polarization of induced dipoles. The model agrees with experimental results for various hi...