In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q inductors can be achieved at higher frequencies while the oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor siz...

This article proposes a general physics-based model for identifying the parasitic capacitance in medium-voltage (MV) filter inductors, which can provide analytical calculations without using empirical equations and is not restricted by geometrical structures of inductors. The elementary capacitances MV inductor are identified, then equivalent between two terminals derived under different voltag...

In this work, we present for the first time, a highly scalable general high voltage MOSFET model, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high ...

This paper presents a method for predicting parasitic capacitances of solenoid HF inductors made of one layer of turns with circular cross sections, uniformly wound around a cylindrical nonconductive core. The method is based on an analytical approach to obtain the turn-to-turn and turn-to-shield capacitances of coils. The influence of the wire insulation is taken into account. An equivalent lu...

This paper presents an exhaustive method to characterize the interconnect capacitances with taking the floating dummy-tills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is implemented into the 3D finite-differe...

This paper examines the recently introduced Charge-Based Capacitance Measurement (CBCM) technique through use of a 3-D interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall c...

In this article the problem of crosstalk noise in integrated circuits is considered. Interconnects are modelled by elementary components. The different models that are able to integrate with precision an interconnection are given. We also exhibit the RC effect followed by the impact of inserting the repeaters in the line. Crosstalk noise in deep submicron integrated circuit is also presented in...

This study proposed a novel 4H-SiC double trench metal-oxide-semiconductor field-effect-transistor (DTMCD-MOSFET) structure with built-in MOS channel diode. Further, its characteristics were analyzed using TCAD simulation. The DTMCD-MOSFET comprised active and dummy gates that divided horizontally; the diode operated through gate p-base N+ source regions at bottom of gate. Because bult-in was p...