Chip multiprocessors (CMPs) with on-chip network connecting processor cores have been pervasively accepted as a promising technology to efficiently utilize the ever increasing density of transistors on a chip. Communications in CMPs require invalidating cached copies of a shared data block. The coherence traffic incurs more and more significant overhead as the number of cores in a CMP increases...

The paper presents a novel Optical Network on Chip (ONoC) relying on the multi-level optical layer design paradigm and called “OMNoC”. The proposed ONoC relies on multi-level microring resonator allowing efficient light coupling between superposed waveguides. Such microring resonator avoids using waveguide crossing, which contribute to reduce propagation losses. Preliminary experimental results...

Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based mult...

Network-on-chip-based multiprocessor systems-onchip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel platform involves scheduling the communication on the network-onchip. This paper presents different scheduling strategies that minimize resource usage by exploiting all scheduling freedom offered by networks-on-chip. It also int...

The scalability of communication infrastructure in modern Integrated Circuits (ICs) becomes a challenging issue, which might be a significant bottleneck if not carefully addressed. Towards this direction, the usage of Networks-on-Chip (NoC) is a preferred solution. In this work, we propose a software-supported framework for quantifying the efficiency of heterogeneous 3-D NoC architectures. In c...

In this paper, a simple and e cient clock boosting mechanism to increase the performance of an adaptive router in Network-on-Chip (NoC) is proposed. One of the most serious disadvantages of a fully adaptive wormhole router is performance degradation due to the routing decision time. The key idea to overcome this shortcoming is the use of di erent clocks in a head it and body its. The simulation...

A TYPICAL ASIC chip today is about 50 square millimeters of silicon containing about 50 million transistors on 130-nm process technology, operating at somewhere between 300 and 500 MHz. These parts come off, literally in the thousands, from 300-mm wafers—and in sufficient quantity cost around $5 each, no matter what you build with the digital CMOS circuits onboard. Thus, in addition to being th...

Wireless communication is becoming more and more important in today’s world. We rely on radio transmission for audio/video broadcasts, telecommunication, satellite navigation, security systems and many wireless sensor devices. These communication systems use reserved parts of the frequency spectrum, to ensure low interference between transmitters and receivers of different communication systems...

In the context of declining Moore and Dennard Laws, efficient utilization of chip area and transistor is more than ever required. The portion of transistors devoted to compute operations can be maximized by off-loading as much as possible data-storage onto memory chips. This, however, requires wide off-chip IO bandwidth, and furthermore increases Network-on-chip (NoC) traffic. In this paper, we...

Today’s System-on-Chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yield, while containing test & repair cost and minimizing time-to-volume. This paper summarizes the evolution of such yield optimization resources, compares their trade-offs, and concentrates on on-chip Infrastructure IP. To maximi...