Efficient route maintenance in DHTs is still an area of very active research due to its complexity and multitude of aspects to be considered. In this paper we propose novel correctionon-failure (CoF) and correction-on-use (CoU) approaches that support route maintenance more efficiently than existing methods even under highly dynamical network conditions. In contrast to previous work which addre...

Communication overheads are one of the most important barriers to efficient parallel execution. In an Explicit Dataflow Graph Execution (EDGE) architecture, communication overheads are particularly important, as communication occurs at an instruction-level granularity. These communication overheads are exposed through the ISA, however, so the compiler can attempt to place instructions in a way ...

Many different sources of overheads impact the efficiency of a scheduling strategy applied to a parallel loop within a scientific application. In prior work, we handled these overheads using multiple loop scheduling strategies, with each scheduling strategy focusing on mitigating a subset of the overheads. However, mitigating the impact of one source of overhead can lead to an increase in the i...

Task-based programming is becoming the state-of-the-art method of choice for extracting the desired performance from multi-core chips. It expresses a program in terms of lightweight logical tasks rather than heavyweight threads. Intel Threading Building Blocks (TBB) is a task-based parallel programming paradigm for multi-core processors. The performance gain of this paradigm depends to a great ...

Most real-time multiprocessor scheduling algorithms for achieving optimal processor utilization, adhere to the fairness rule. Accordingly, tasks are executed in proportion to their utilizations at each time quantum or at the end of each time slice in a fluid schedule model. Obeying the fairness rule results in a large number of scheduling overheads, which affect the practicality of the algorith...

The soft error rates (SER) in logic circuits increase quickly as devices scale. Existing techniques to mitigate soft errors in logic circuits often incur large overheads. In this work, we propose a ’lightweight’ technique that detects soft errors in logic circuits, utilizing the concept of temporal sampling. The technique adds some modifications to the conventional pipeline to allow data to be ...

A list of technical reports, including some abstracts and copies of some full reports may be found at: Abstract. Software overheads can be a signiicant cause of performance degradation in parallel numerical libraries. This paper examines the nature and extent of software overheads in an implementation of parallel LAPACK on distributed memory multiprocessors, where block-partitioned algorithms w...