We study the computational power of shallow quantum circuits with n input qubits, one output qubit, and two types of ancillary qubits: O(log n) initialized and O(poly(n)) uninitialized qubits. The initial state of the uninitialized ancillary qubits is arbitrary, and we have to return their state into the initial one at the end of the computation. First, to show the strengths of such circuits, w...

We present a technique to derive depth lower bounds for quantum circuits. The technique is based on the observation that in circuits without ancillæ, only a few input states can set all the control qubits of a Toffoli gate to 1. This can be used to selectively remove large Toffoli gates from a quantum circuit while keeping the cumulative error low. We use the technique to give another proof tha...

This paper presents a new simple and straightforward method for designing Self-Testing Embedded (STE) parity checkers. The building block is the two-input XOR gate. During normal, fault-free operation, each XOR gate receives all possible input vectors. The great advantage of the proposed method is that it is the only one that gives, in a simple and straightforward way, optimal STE realizations ...

We initiate the study of quantifying the quantumness of a quantum circuit by the number of gates that do not preserve the computational basis, as a means to understand the nature of quantum algorithmic speedups. Intuitively, a reduction in the quantumness requires an increase in the amount of classical computation, thus giving a “quantum and classical tradeoff”. In this paper we present two res...

We present a technique to derive depth lower bounds for quantum circuits. The technique is based on the observation that in circuits without ancillæ, only a few input states can set all the control qubits of a To↵oli gate to 1. This can be used to selectively remove large To↵oli gates from a quantum circuit while keeping the cumulative error low. We use the technique to give another proof that ...

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a s...

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean f...

It was recently noted how the classical sine-Gordon theory can support discontinuities, or ‘defects’, and yet maintain integrability by preserving sufficiently many conservation laws. Since soliton number is not preserved by a defect, a possible application to the construction of logical gates is suggested. a E-mails: [email protected]; [email protected]