Asynchronous pipelining is a form of parallelism which may be used in distributed memory systems. An asynchronous pipeline schedule is a generalization of a noniterative DAG schedule. Accurate estimation of the execution time of a pipeline schedule is needed to determine if pipelining is appropriate for a loop, and to compare alternative schedules. Pipeline execution of n iterations of a loop r...

Loops with conditional branches have multiple execution paths which are diicult to software pipeline. The mod-ulo scheduling technique for software pipelining addresses this problem by converting loops with conditional branches into straight-line code before scheduling. In this paper we present an Enhanced Modulo Scheduling (EMS) technique that can achieve a lower minimum Initiation Interval th...

Pipelined computing is a promising paradigm for embedded system design. Designing the scheduling policy for a pipelined system is however more involved. In this paper, we study the problem of the energy minimization for coarse-grained pipelined systems under hard real-time constraints and propose a method based on an inverse use of the pay-burst-only-once principle. We formulate the problem by ...

In this paper, we address the integration of production planning and reactive scheduling for the optimization of a hydrogen supply network consisting of five plants, four inter-connected pipelines and 20 customers. We present multiperiod mixed integer nonlinear programming (MINLP) models for both the planning and scheduling levels. The planning model includes complex pricing functions resulting...

Mainstream operating systems are starting to face the need for support of multi-core platforms. We argue that pipeline parallelism is one of the practical ways to utilize performance offered by multiple cores with minimal changes to the existing software stack. Similar to the organization of hardware processors, execution of a system can be structured as a set of pipeline stages running in para...

The unpredictable nature of modern workloads, characterized by frequent branches and control transfers, can result in processor pipeline utilization as low as 19%. Chip multithreading (CMT), a processor architecture combining chip multiprocessing and hardware multithreading, is designed to address this issue. Hardware vendors plan to ship CMT systems within the next year, so now is the time for...

We present Piko, a framework for designing, optimizing, and retargeting implementations of graphics pipelines on multiple architectures. Piko programmers express a graphics pipeline by organizing the computation within each stage into spatial bins and specifying a scheduling preference for these bins. Our compiler, Pikoc, compiles this input into an optimized implementation targeted to a massiv...