نتایج جستجو برای: pipelining

تعداد نتایج: 1926  

Journal: :IEEE Transactions on Computers 2007

2009
Leonardo Scandolo César Kunz Manuel V. Hermenegildo

While there are well-understood methods for detecting loops whose iterations are independent and parallelizing them, there are comparatively fewer proposals that support parallel execution of a sequence of loops or nested loops in the case where such loops have dependencies among them. This paper introduces a refined notion of independence, called eventual independence, that in its simplest for...

1998
John B. Pormann

We present a novel scheme for the solution of linear differential equation systems on parallel computers. The Implicit Pipeline (ImP) method uses an implicit timeintegration scheme coupled with an iterative linear solver to solve the resulting differential algebraic system. The ImP method then allows for two independent mechanisms for parallelism: pipelining of the solution of several timesteps...

1993
Naresh R. Shanbhag Keshab K. Parhi

A fine-grain pipelined adaptive differential vector quantizer architecture i s proposed f o r low-power speech coding applications. T h e pipelined architecture is developed by employing the relaxed look-ahead technique. The hardware overhead due t o pipelining i s only the pipelining latches. Simulat ions with speech sampled at 8 h'hz show that , f o r a vector dimension o 8, the degradation i...

2010
Frédéric Brault Albert Cohen

Embedding register-pressure control in software pipelining heuristics is the dominant approach in modern back-end compilers. However, aggressive attempts at combining resource and register constraints in software pipelining have failed to scale to real-life loops, leaving weaker heuristics as the only practical solutions. We propose a decoupled approach where register pressure is controlled bef...

2001
Reza Hashemian

Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

2008
Cody Hartwig Elie Krevat

Modern processors, especially VLIW processors, often have the ability to execute multiple instructions simultaneously. Taking advantage of this capability is crucial for high performance software applications. Software pipelining is a technique designed to increase the level of parallelism in loops. We propose a new approach to software pipelining based on direct manipulations of control flow g...

1994
Sissades Tongsima Nelson L. Passos Edwin Hsing-Mean Sha

Sissades Tongsima Nelson L. Passos Edwin H-M. Sha Dept. of Computer Science & Engineering University of Notre Dame Notre Dame, IN 46556 Abstract Loop pipelining (retiming) is a valuable tool used to explore parallelism across iterations. Few results are available about loop pipelining with data communication considerations. This paper rst designs a modi ed list scheduling algorithm to be used a...

2009
Kavita Khare Nilay Khare

The IEEE-754 standard floating point multiplier that provides highly precise computations to achieve high throughput and low area on the IC have been improved by insertion of pipelining technique. Floating point multiplier-using pipelining has been simulated, analyzed and its superiority over traditional designs is discussed. To achieve pipelining, one must subdivide the input process into sequ...

نمودار تعداد نتایج جستجو در هر سال

با کلیک روی نمودار نتایج را به سال انتشار فیلتر کنید