A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology has been presented in this paper. The main advantage of the proposed scheme is its improved speed performance compared with previous designs. With the help of modifications applied to the encoder section using Pass Transistor Logic (PTL), the corresponding capacitances o...

Background and Objectives: In recent decades, due to the effect of the short channel, the use of CMOS transistors in the nanoscale has become a major concern. One option to deal with this issue is the use of nano-transistors. Methods: Using nano-transistors and multi-valued logic (MVL) can reduce the level of chips and connections and have a direct impact on power consumption. The present study...

Modulo 2+1 multiplier is one of the critical components in the area of digital signal processing, residue arithmetic, and data encryption that demand high-speed and low-power operation. In this paper, a new circuit implementation of a high-speed low-power modulo 2+1 multiplier is proposed. It has three major stages: partial product generation stage, partial product reduction stage, and the fina...

The main objective of this paper was to analyze the best possible implementation style for the data path designs so as to optimize their performance according to the application domain as well as field of use. In this project, we present the design and analysis of two new processing elements for reconfigurable computing. We also present a circuit-level implementation of the data paths in static...

We present a statistical model for the delay profile of ultra-wideband channels in indoor environments. Two kinds of profiles are defined, namely the multipath intensity profile (MIP) and the power delay profile (PDP). The MIP is he delay profile at a point in space, while the PDP is a local spatial average. The model is based on 60,000 complex frequency response measurements from 20 commercial...

Received Apr 24, 2016 Revised Aug 3, 2016 Accepted Aug 18, 2016 In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4-2 compressors and 5-2 compressors are extensively utilized for numerical realizations. Both the compressors circuits that is the 4-2 compressor circuit and 5-2 compressor circuit internally consist of the logic gates i.e. the XOR an...

This paper present new energy efficient methods of designing switches and routing interconnects inside FPGA using novel variants of Dynamic Threshold MOS (DTMOS) instead of traditional NMOS pass transistor based switches and interconnects. The extra needed transistors can be easily shared, in multiplexer based routing architecture of FPGA, keeping area overhead to be minimum. Extensive transist...

This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy eff...

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of flip-flops. carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optim...

In this paper, we propose a novel multiplexer-based full adder design, denoted as MUXFA, by using regular modules for arithmetic applications. The MUXFA full adder is composed of three identical modules, in which each module separately operates for XOR-XNOR function, sum function, and carry function. The structure of the multiplexer-based full adder can be easily constructed by merely a single ...