A list scheduling approach is proposed in this paper to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the list scheduling algorithm in order to improve the test concurrency having assigned power dissipation limits. Moreover, the algorithm features a power dissipation balancing...

Abstract. Recently, many reactance-less memristive relaxation oscillators were introduced, where the charging and discharging processes depend on memristors. In this paper, we investigate the power dissipation in different memristor based relaxation oscillators. General expressions for these memristive circuits as well as the power dissipation formulas for three different topologies are derived...

Chip Interconnect delay and power is a primary criterion in the design of an Integrated Circuit because of its close connection to the speed of IC. Interconnect Buffers in VLSI circuits is the most widespread procedure used to decrease power and delay but they outcome in high Delay and power dissipation, thereby degrading the performance (i.e.) operating speed of an integrated circuit. Use of b...

With the increasing clock rate and transistor count of today’s microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. With the increasing usage...

In this paper, we address three issues related to the design of opamps for oversampled converters: the theoretical minimum-power bound for an ideal opamp, the best opamp choice in terms of power dissipation, and the best design strategy to reduce power dissipation. To be able to do so, we develop a model that captures the dynamics of the integrator inside the modulator. Based on this model, pow...

1 This research was supported in part by DARPA PAC/C program under contract DAAB07-02-C-P302 and by NSF under grant no. 9988441. ABSTRACT Leakage power and hot-carrier effects are emerging as key concerns in deep sub-micron CMOS technologies with respect to their effects on the total power dissipation and reliability of VLSI circuits. Leakage power dissipation is rapidly becoming a substantial ...

Abstract: In today’s world power dissipation is the main problem in digital world; this problem can be reduced by using reversible logic gates. For high performance systems, low power and smaller area are the most important criteria. Area and speed are main factors which are conflicting i.e. if speed is improving it results in larger area, hence in this paper reversible logic gates are analyzed...

This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect...

Digital circuit design is streamlined process used to improve the performance of a circuit for a particular application. Fast speed, minimum power dissipation and less area are the desirable characteristics of a digital circuit, in general. To meet a particular standard of speed, a compromise in power dissipation and speed is required. Timing elements such as Flip-flop are used as clock generat...

The study of the power dissipation sources of CMOS circuits is presented. Specifically, the main principles of dynamic, short-circuit, static, and leakage power dissipation are illustrated together with the low power strategies for reducing each power component. Furthermore, we enlighten to some innovative techniques of power reduction, which are based on multiple supply voltages and multiple t...