In this paper, we study sequences generated by arbitrary feedback registers (not necessarily feedback shift registers) with arbitrary feedforward functions. We generalize the definition of linear complexity of a sequence to the notions of strong and weak linear complexity of feedback registers. A technique for finding upper bounds for the strong linear complexities of such registers is develope...

Distributed storage algorithms implement the abstraction of a shared register over distributed base objects. We study a specific class of storage algorithms, which we call amnesic: these have the pragmatic property that old values written in the implemented register might be eventually forgotten, i.e., they are not permanently kept in the storage and might be overwritten in the base objects by ...

This architecture features new mechanisms for the issuing and management of instructions in multi-cluster microarchitectures for superscalar microprocessors. Multi-cluster microarchitectures offer the potential for very substantial reductions in the energy expended per instruction executed, resulting in lower power microprocessors for many applications. Such gains are achieved by partitioning t...

This paper presents an architecture for programmable systolic arrays that provides simple and eecient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board.

This study aimed to assess the quality of Persian translation of Orwell's (1949) Nineteen Eighty-Four by Balooch (2004) based on House's (1997) model of translation quality assessment. To do so, 23 pages (about 10 percent) of the source text were randomly selected. The profile of the source text register was produced and the genre was realized. The source text profile was compared to t...

We introduce a new kind of word-oriented linear feedback shift register called σ−LFSR which is constructed with the instructions of the modern processor and have fast software implementation. We offer an algorithm to search for good primitive σ−LFSR. In particular, we give two examples HHZ-1 and HHZ-2 and compare their efficiency and security with those of the LFSRs appearing in stream ciphers ...

Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to r...

Programs with dynamic allocation are able to create and use an unbounded number of fresh resources, such as references, objects, files, etc. We propose History-Register Automata (HRA), a new automata-theoretic formalism for modelling such programs. HRAs extend the expressiveness of previous approaches and bring us to the limits of decidability for reachability checks. The distinctive feature of...

Served as one of the most widely used wireless airlink interface, CDMA has been identified as a major technique for 3G wireless communications. The current IS-95 CDMA provides a near-satisfactory security solution to voice centric wireless communications, since generally each voice conversation only lasts a very short period of time. However, the security features provided by IS-95 CDMA are far...

Arithmetic function modules which are available in many circuits can be utilized to generate test patterns and compact test responses. Recently, it was shown that an adder or an accumulator cannot be used as a bit serial test pattern generator due to the poor random properties of the generated sequences. Thus, accumulator-multiplier or adder-multiplier structures have been proposed. In this pap...