Reversible circuits for SR ip op, JK ip op, D ip op, T ip op, Master Slave D ip op and Master Slave JK ip op have been provided with three di erent logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier propos...

Reversible sequential circuits are going to be the significant memory blocks for the forthcoming computing devices for their ultra low power consumption. Therefore design of various types of latches has been considered a major objective for the researchers quite a long time. In this paper we proposed efficient design of reversible sequential circuits that are optimized in terms of quantum cost,...

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...

We propose a new family of quantum computing algorithms which generalize the Deutsch-Jozsa, Simon and Shor ones. The goal of our algorithms is to estimate conditional probability distributions. Such estimates are useful in applications of Decision Theory and Artificial Intelligence, where inferences are made based on uncertain knowledge. The family of algorithms that we propose is based on a co...

Reversible single-target gates are a generalization of Toffoli gates which are a helpful formal representation for the description of synthesis algorithms but are too general for an actual implementation based on some technology. There is an exponential lower bound on the number of Toffoli gates required to implement any reversible function, however, there is also a linear upper bound on the nu...

It is a widely supported prediction that conventional computer hardware technologies are going to reach their limits in the near future. Thus, to further satisfy the needs for more computational power, alternatives are required that go beyond the scope of conventional technologies. Reversible logic marks a promising new direction where all operations are performed in an invertible manner [1]. T...

An efficient hardware implementation of FFT algorithm become essential one in signal analysis domain, more specifically the twiddle factor calculation in FFT computation plays important role in the speed and efficiency of the complete process. World of computation needs the fast and efficient tools to match the need of present scenario, even though there are many methods proposed the Reversible...

We develop a framework for resource efficient compilation of higher-level programs into lower-level reversible circuits. Our main focus is on optimizing the memory footprint of the resulting reversible networks. This is motivated by the limited availability of qubits for the foreseeable future. We apply three main techniques to keep the number of required qubits small when computing classical, ...

Overcoming the IC power challenge requires signal energy recovery, which can be achieved utilizing adiabatic charging principles and logically reversible computing in the circuit design. This paper demonstrates the energyefficiency of a Bennett-clocked adiabatic CMOS multiplier via a simulation model. The design is analyzed on the logic gate level to determine an estimate for the number of irre...

Whereas quantum computing circuits follow the symmetries of the unitary Lie group, classical reversible computation circuits follow the symmetries of a finite group, i.e., the symmetric group. We confront the decomposition of an arbitrary classical reversible circuit with w bits and the decomposition of an arbitrary quantum circuit with w qubits. Both decompositions use the control gate as buil...