InGaAs PIN photodetectors heterogeneously integrated on silicon-on-insulator waveguides are fabricated and characterized. Efficient evanescent coupling between silicon-on-insulator waveguides and InGaAs photodetectors is achieved. The fabricated photodetectors can work well without external bias and have a very low dark current of 10pA. The measured responsivity of a 40microm-long photodetector...

Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we de...

We have analyzed the dominant noise sources in the driving circuit of an uncooled infrared radiation focal plane array fabricated on a silicon-on-insulator (SOI) substrate by 0.35 μm CMOS technology and bulkmicromachining. We found no noise property of SOI-MOSFET inferior compared to those of NMOSs formed on SOI and bulk substrate, respectively. In addition, we reduced the total noise of the se...

Demonstrations of sub 20nm gate length MOSFET devices involving various FEOL (front end of line) schemes such as Silicon On DEpletion Layer (SODEL) FET’s, asymmetricgate FinFET devices, planar Ultra-thin body SOI (UTSOI) FET’s, and, more recently, independently oriented surface channels for (110) pMOS and (100) nMOS described as Simplified Hybrid Orientation Technology (SHOT).[1-4, 718] have be...

We have been developing the monolithic active pixel detector "XRPIX" onboard future X-ray astronomical satellite "FORCE". XRPIX is composed of CMOS circuits, SiO2 insulator, and Si sensor by utilizing silicon-on-insulator (SOI) technology. When semiconductor operated in orbit, it suffers from radiation damage due to X-rays emitted celestial objects as well cosmic rays. From previous studies, po...

We investigate thermal noise mechanisms and present analytical expressions of the noise power spectral density at high frequencies (HF) in Silicon-on-insulator (SOI) MOSFETs. The developed HF noise model of RF T-gate body contact (TB) SOI MOSFET for 0.13-μm SOI CMOS technology accounts for the mechanisms of 1) channel thermal noise; 2) induced gate noise; 3) substrate resistance noise and 4) ga...

This paper presents a new, simple method of measuring the generation lifetime in SOI (silicon-on-insulator) MOSFETS. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across ®nished SIMOX (separation by implantated oxygen) wafers, BESOI (bonded and etchedback SOI) wafers, and UNIBOND wafers. BESOI materi...

We present the design, fabrication and characterization of efficient fiber-to-chip grating couplers on a Germanium-on-Silicon (Ge-on-Si) and Germanium-on-silicon-on-insulator (Ge-on-SOI) platform in the 5 µm wavelength range. The best grating couplers on Ge-on-Si and Ge-on-SOI have simulated coupling efficiencies of -4 dB (40%) with a 3 dB bandwidth of 180 nm and -1.5 dB (70%) with a 3 dB bandw...

Abstract When silicon-on-insulator p-type MOSFET (SOI-PMOS) functions like a capacitor-less 1T-DRAM cell, it is possible for the number of electrons to be sensed at cryogenic temperatures (5 K). We developed structure that combines n-type MOSFETs (SOI-NMOS) and SOI-PMOS with multiple gates form silicon quantum-dot array. In this structure, variable injected into body by means bucket-brigade ope...

Silicon On Insulator (SOI) can leverage a lot of new advantages for circuit designers compared to conventional bulk technology. In particular, the improved S-factor and reduced junction capacitance make it very appealing for next generation low power, high performance DRAM systems. However, the benefits of the SOI technology do not come entirely for free. In this project, we characterized the k...