This article describes a new paradigm in the design of soft error resilient architectures involving reuse of on-chip resources for multiple functions at various stages of manufacturing and field use. For example, on-chip Design for Testability resources for scan can be reused for soft error protection during normal operation. We focus on the sequential elements (flip-flops and latches) of a des...

Soft errors are a growing concern for processor reliability. Recent work has motivated architecture level studies of soft errors since the architecture level can mask many raw errors and architectural solutions can exploit workload knowledge. My dissertation focuses on the modeling and analysis of soft error issues at the architecture level. We start with the widely used method for estimating t...

Device scaling has caused the challenges that processor designers face to evolve significantly in the past. This trend will continue into the future, and reliability is emerging as a significant challenge. In this work, we focus on one aspect of the reliability problem: soft errors. In particular, cost effective mitigation of soft errors in processor microarchitecture. Our investigation begins ...

This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft error on the internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from particle hit on combinational logic. The proposed circuit has low power consumption with negative se...

other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Summary A soft error in configuration memory can corrupt a design. However, the proper operation of a typical design loaded into a Xilinx FPGA only involves a fraction of the total number of configuration memory cells. This ...

As technology scales, VLSI performance has experienced an exponential growth. As feature sizes shrink, however, we will face new challenges such as soft errors (single-event upsets) to maintain the reliability of circuits. Recent studies have tried to address soft errors with error detection and correction techniques such as error correcting codes and redundant execution. However, these techniq...

In the multi-peta-flop era for supercomputers, the number of computing cores is growing exponentially. However, with integrated circuit technology scaling below 65 nm, the critical charge required to flip a gate or a memory cell is dangerously reduced. Combined with higher vulnerability to cosmic radiation, soft errors are expected to become anything but inevitable for modern supercomputer syst...

the main objective of this study is to swing krull intersection theorem in primary decomposition of rings and modules to the primary decomposition of soft rings and soft modules. to fulfill this aim several notions like soft prime ideals, soft maximal ideals, soft primary ideals, and soft radical ideals are introduced for a soft ring over a given unitary commutative ring. consequently, the p...