Contemporary inquisition on numerous schemas of FPGA endeavoring curtailment of power consumption effectuates the inference that one of the utmost expansively used contexts is Static Random Access Memory (SRAM) based structures. This paper addresses the limitations associated with SRAM such as low density, longer routing path, increased propagation delay, increased peak power consumption rate a...

In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses. The cell structure of the proposed SRAM has two high-value resistors based on a p-type metal-oxide semiconductor transistor, a cross-coupled n-type metal-oxide semiconductor (...

In this field research paper explores the design and analysis of Static Random Access memories (SRAMs) that focuses on optimizing delay and power. CMOS SRAM cell consumes very less power and have less read and write time. Higher cell ratios will decrease the read and write time and improve stability. PMOS semiconductor unit with fewer dimensions reduces the ability consumption. During this pape...

In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression drive...

Memory is an important part of any electronic device. In today's world static random access memory (SRAM) is widely used as memory. The major issues for design of SRAM are power loss, delay and stability. This paper presents a modified form of a symmetric eight-transistor SRAM bit-cell. In this paper transmission gate has been used as access transistor which provides rail-to-rail swing. Moreove...

This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% ...

microprocessor and cache subsystem F. Busaba M. A. Blake B. Curran M. Fee C. Jacobi P.-K. Mak B. R. Prasky C. R. Walters The IBM zEnterpriseA 196 (z196) system, announced in the second quarter of 2010, is the latest generation of the IBM System zA mainframe. The system is designed with a new microprocessor and memory subsystems, which distinguishes it from its z10A predecessor. The system has u...

In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes...

Our present research endeavor focuses on the factors of hybrid single electron transistor (SET)-CMOS based static random access memory (SRAM). Ultra small low power dissipated SET is combined with high gain and high current drivable CMOS and the write operation of the memory cell is briefly analyzed. This work is a comparative work of power consumption between conventional CMOS based SRAM and h...

With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM’s. We present techniques based on replica circuits which minimize the effect of operating conditions’ variability on the speed and power. Replica memory cells and bitlines are used to create a reference...