Power consumption can be greatly minimized by reducing the bus signal transition activity (also called switching activity) in the control and data path circuit. Switching activity occurs due to the switching between two instructions (of the embedded software) on successive clock cycles. Our belief is that the binary encoding of instructions (machine code) plays a significant role in determining...

Symbolic analysis methods for averaged modeling of switching power converters are presented in this paper. A general averaging method suitable for computer-aided modeling is discussed first. Then, a symbolic analysis package that uses this averaging method to automatically generate an analytical averaged model for a switching power converter is described. The package is implemented using the co...

This document provides an overview of a novel approach to network layer packet forwarding, called tag switching. The two main components of the tag switching architecture forwarding and control are described. Forwarding is accomplished using simple label-swapping techniques, while the existing network layer routing protocols plus mechanisms for binding and distributing tags are used for control...

Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability ar...

We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), lo...

Low power VLSI testing is indispensible in switching components and number of hardware/software-based techniques has been still developed to minimize the dynamic power dissipation. In earlier days, primary concerns of VLSI design were focused in area, performance, cost and reliability. But in current years, the design constraints have begun to change because of increasing low power testing. XOR...

Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability ar...

Effective mode-switching techniques provide users of tablet interfaces with access to a rich set of behaviors. While many researchers have studied the relative performance of mode-switching techniques in these interfaces, these metrics tell us little about the behavior of one technique in the absence of a competitor. Differing from past comparison-based research, this paper describes a temporal...

This paper investigates performance evaluation of Asynchronous Transfer Mode (ATM) switching systems: Private Branch Exchanges (PBX), switches and cross-connects. The performance evaluation of ATM switching systems is not as straightforward as one might expect. This is due to the fact that performance can be seen from different angles. The measurements presented in this paper include: throughpu...