A concept for solving the communication problem among modules dynamically placed on a reconfigurable device is presented. Based on a dynamic network-on-chip (DyNoC) communication infrastructure, components placed at run-time on a device can mutually communicate. A 4x4 dynamic network-on-chip communication infrastructure prototype, implemented in an FPGA occupies only 7% of the device area and c...

To build a system-on-chip (SoC) a common interface standard is necessary to connect ready-to-use components (IPs) from different vendors. Today several SoC interconnect standards, such as AMBA, Wishbone, OPB, and Avalon, are in use. We show in this paper that those standards have a common drawback for on-chip interconnections: They are built on the model of a common backplane bus that does not ...

ABSTRACT: A multiresolution AHB on-chip bus tracer named SYS-HMRBT (AHB multiresolution bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. Experiments show that the bus tracer achieves very good compression r...

Clocking considerations and clocked storage elements for System on a Chip are discussed. Various ways of SOC clocking are addressed. We discuss issues of particular importance for SOC such as “time borrowing” and absorption of clock uncertainties. Clock power savings techniques suitable for SOC are described.

The paper describes the need for early analysis tools to enable developers of today’s system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs an...

Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance evaluation of On-Chip Interconnect (OCI) architectures is widely based on simulation which becomes computationally expensive, especially for largescale NoCs. In this paper, we study

SULE, AMBARISH MUKUND Hardware-Software Codesign of a Programmable Wireless Receiver System-on-a-chip. (Under the direction of Prof. William Rhett Davis). With gate counts and system complexity growing rapidly, engineers have to find efficient ways of designing hardware circuits. The advent of Hardware Description Languages and synthesis methodologies improved designer productivity by raising t...

With the advances of chip manufacturing technologies, computer architects have been able to integrate an increasing number processors and other heterogeneous components on same chip. Network-on-Chip (NoC) is widely employed by multicore System-on-Chip (SoC) architectures cater their communication requirements. NoC has received significant attention from both attackers defenders. The increased u...

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication p...