For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to ...

BIST is a technique aimed to: Avoiding the usage of expensive ATE Increase the fault tolerance since it add more access to the internal points Allow the application of at-speed test and reduce the test time. It is mandatory to consider the BIST as a test solution when the design flow and the design area can afford it.

The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable Gate Arrays (FPGAs) are described. These BIST configurations completely test the programmable logic and routing resources in the core of the FPGA along with the dedicated Random Access Memories (RAMs) dispersed within the array. The BIST configurations are generated usi...

Structural testing with both scan test and Built-in Self-Test (BIST) has proven effective for detecting both gross static and at-speed defects. As tools and techniques improve, structural testing is approaching the high level of test quality necessary to eliminate test escapes. However, scan and BIST do not accomplish all that is needed. Parametric and functional tests are still needed for adva...

In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the pr...

A Built-In Self-Test (BIST) approach for the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs) is presented. The I/O buffers are tested for their various modes of operation along with their associated routing sources. A general BIST architecture, applicable to any FPGA, is presented along with the features and limitations of the approach. Experimental results are...

The increasing growth of sub-micron technology has resulted in the difficulty of VLSI testing. Test and design for testability are recognized today as critical to a successful design. Built-in-SelfTest (BIST) is becoming an alternative solution to the rising costs of external electrical testing and increasing complexity of devices Small increase in the cost of system reduces large testing cost....

Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only interna...

A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide...

A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan circuits, together with necessary supplementary algorithms, is proposed in this Thesis. This method is mostly based on a design of a combinational block the Decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by some ATPG tool. The Column-Matching algo...