The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO’s) is investigated in order to clarify the lower limit of supply voltage (VDD) for logic circuits. The measured VDDmin is determined by the intra-die threshold voltage random variations and increased from 91 mV to 224 mV when the number of RO stages increased from 11 to 1001, which hinders the VDD scaling. Lowering VDDmin...

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the ...

The phase noise in an ultra low-power and low-voltage CMOS voltage controlled oscillator (VCO) has been measured and modelled for supply voltage VDD from 1.8 V down to 80 mV with various body bias voltages V B ~ The VCO is a fully integrated ring oscillator designed in a 0.18pm CMOS technology. In this design, the frequency can be controlled by VBp The effects of scaling VDD together with the e...

This paper investigates the optimization of sleep mode energy consumption for ultra-low Vdd CMOS circuits, which is motivated by our findings that minimization of sleep mode energy holds great potential for reducing total energy consumption. We propose a unique approach of using a power gating switch (PGS) in ultra-low Vdd regimes. Unlike the conventional manner of using PGSs, our optimization ...

In this paper, dynamic algorithm transformations (DAT’s) for designing low-power reconfigurable signal-processing systems are presented. These transformations minimize energy dissipation while maintaining a specified level of mean squared error or signal-to-noise ratio. This is achieved by modeling the nonstationarities in the input as temporal/spatial transitions between states in the input st...

Objective: To determine how short and long term complication rates after pacemaker implantation are influenced by patient morbidity, operator experience, and choice of pacing system. Design: Retrospective analysis of 1884 patients who received VVI (n = 610), VDD (n = 371), or DDD devices (n = 903) between 1990 and 2001. Follow up period was 64 (34) months. The influence of age, sex, coronary ar...

Energy harvesting systems suffer variable power supply from time to time. Ultra low power supply or even a very short period without power supply may cause very serious consequences. In the case of system memories, important data may be lost. A gated diode based DRAM can be a potential memory solution as a dynamic backup storage to meet these challenges. However, before exploring this solution,...

On-chip memories generally use higher supply (VDD) and higher threshold (Vth) voltages than those of logic parts to improve the static noise margin and to suppress the static energy consumption. However, the higher VDD increases the dynamic energy consumption. This paper proposes a hybrid memory architecture which consists of the following two regions; (1) a dynamic energy conscious region whic...

Portable electronic systems require low-voltage low-power building blocks. An important building block is an A/D converter. ∆Σ ADCs provide an efficient way of trading off speed for resolution. The switched opamp (SO) technique allows design of switched-capacitor (SC) circuits at very low supply voltage without the use of multithreshold technologies or voltage multipliers to drive the switches ...

RC Relaxation Oscillators (RxO) are attractive for integrated clock sources compared to LC and ring oscillators (RO), as LC oscillators pose integration challenges and RO designs have limited voltage and temperature (V-T) stability. RxOs generate a clock whose time period (TP) depends only on the timing resistor (R) and capacitor (C). Ideally, TP is independent of V-T; however, most RxOs use a ...