Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hardware. However, control and data dependencies between operations limit the available ILP, which not only hinders the scalability of VLIW architectures, but also result in code size expansion. Although speculation and p...

To process enormous multimedia data, we have designed a VLIW (Very Long Instruction Word) processor called FLOVA (FLOating-Point VLIW Architecture) exploiting the ILP (Instruction-Level Parallelism) in multimedia programs. FLOVA executes four instructions simultaneously in one cycle and supports 136 instructions including 35 media instructions to accelerate multimedia programs. This paper prese...

This report discusses the similarities and the differences betweenmachine scheduling problems, and instruction scheduling problems on modern VLIW processors such as the STMicroelectronics ST200. Our motivations are to apply the machine scheduling techniques that are relevant to instruction scheduling in VLIW compilers, and to understand how processor micro-architecture features impact advanced ...

This paper presents the implementation of the processor of the Image Processing parallel architecture GFLOPS. This processor is a RISC/VLIW. The network module associated in the chip is such that it is possible to build a large architecture by the juxtaposition of as many chips as required. An evaluation of this architecture is presented at the end of this paper through the use of simulation re...

Hardware multithreading is a well-known technique to increase the utilization of processor resources. However, most studies have focused on superscalar processor organizations. This paper analyzes which type of hardware multithreading is most suitable for a VLIW architecture and proposes two buffers to increase the efficiency of hardware multithreading. An important goal of our work is that no ...

High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar ar...

An optimizing compiler, which generates tree instructions in a VLlW assembly language. A translator from VLlW assembly code into PowerPC@ assembly code which emulates the functionality of the VLlW processor for the specific VLlW program. The emulating code also includes instrumentation for collecting execution counts of VLIWs, profiling information, and generation of predecoded execution traces...

Media processing has motivated strong changes in the focus and design of processors. The inclusion of μSIMD multimedia extensions such as MMX is a cost effective option to improve the performance of those regions of the program with large amounts of DLP. This paper provides an initial evaluation of μSIMD and vector-SIMD enhanced VLIW architectures. We show that these two architectures execute r...

VLIW processors have started gaining acceptance in the embedded systems domain. However, monolithic register file VLIW processors with a large number of functional units are not viable. This is because of the need for a large number of ports to support FU requirements, which makes them expensive and extremely slow. A simple solution is to break up this register file into a number of small regis...