In the companion paper, we addressed the low-power DCT/IDCT VLSI architectures of linear complexity increase based on the multirate approach. In this paper, we will discuss other aspects of the low-power design. Firstly, we consider the design of low-power architectures that can lower the power consumption at only O(log M) increase in hardware complexity. Next, we will extend the low-power DCT ...

This paper introduces a method for extracting the core of a Residue Number System (RNS) number within the RNS, this affording a new method for scaling RNS numbers. Suppose an RNS comprises a set of co-prime moduli, mi, with ∏mi = M. This paper describes a method for approximately scaling such an RNS number by a subset of the moduli, ∏mj = MJ ≈ √M, with the characteristic that all computations a...

This paper presents two techniques for the design of digital filters with wordlength-constrained coefficients, the bit-flipping algorithm improved since it was first presented in [l] and the Downhill Simplex Method [2] modified to deliver fixed-point filter coefficients. Both techniques can be applied to design of filter coefficients from scratch or to the optimisation of their floatingpoint ve...

In this paper, we develop a novel 8 8 twodimensional (2-D) discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture based on the direct 2-D approach and the rotation technique. The computational complexity is reduced by taking advantage of the special attribute of complex number. Both the parallel and the folded architectures are proposed. Unlike other approaches, the...

In this paper, Bireciprocal Lattice Wave Digital Filters (BLWDFs) are utilized in an approximate linear phase design of 9 th order IIR wavelet filter banks (FBs). Each of the two branches in the structure of the BLWDF realizes an Allpass filter. The low-coefficient sensitivity, excellent dynamic range and good stability properties of such filters allow their realization with short coefficient w...

In this paper, a new technique is presented for the design and optimization of digital FIR filters with coefficients that are presented in canonic signed-digit (CSD) format. Since such implementation requires no multipliers, it reduces the hardware cost and lowers the power consumption. The proposed technique considers three goals, the optimum number of coefficients, the optimum wordlength, and...

(ii) Use of multiplier blocks can drastically change the complexity relations between different structures. Despite using almost twice the wordlength, and many more coefficients (corresponding to having almost 2.5 times the complexity using the C, measure), the direct forms require similar numbers of adders to the waveform. Similarly, but less dramatically, the cascade and parallel forms are si...

In this paper an improved method of design of low sensitivity multiplierless elliptic IIR digital filters is proposed. The design technique is based on the sensitivity analysis and a selection of proper allpass sections. The allpass sections used to realize the allpass structures are with minimized sensitivities. Using the symbolic analysis, the expressions for phase sensitivities to multiplier...

This paper is a study of high-throughput filter structures such as block structures and their behavior in finite precision environments. Block structures achieve high throughput rates by using a large number of processors working in parallel. It has been believed that block structures which are relatively robust to round-off noise must also be robust to coefficient quantization errors. However,...

Abstmct-Researchers in digital signal processing have examined at length the effects of finite wordlength in the design of digital filters. The issues that have been considered apply to any digital system. In particular, the design of digital control systems must consider these issues. In this paper we will use, adapt, and extend the ideas developed in digital signal processing to the issue of ...