This paper presents a method for optimizing register allocation for processors which can reconfigure their access to different register banks to increase the number of accessible registers. Register allocation like the graph coloring method of Chaitin aim at keeping a large number of values in registers and minimize the amount of necessary spill code. We extend that method in two directions: Fi...

The stack-based floating point unit (FPU) in the x86 architecture limits its floating point (FP) performance. The flat register file can improve FP performance but affect x86 compatibility. This paper presents an optimized two-phase floating point register renaming scheme used in implementing an x86-compliant processor. The two-phase renaming scheme eliminates the implicit dependencies between ...

BACKGROUND Although the Netherlands currently has its own procedure for evaluating chemical compounds and setting occupational exposure limits (OELs), most of these limits were originally adopted in the 1970s from threshold limit values (TLVs) set by the American Conference of Governmental Industrial Hygienists (ACGIH). However, beginning in the late 1980s, criticism about non-scientific consid...

The computational efficiency and energy-to-solution of several applications using the GAMESS quantum chemistry suite of codes is evaluated for 32-bit and 64-bit ARM-based computers, and compared to an x86 machine. The x86 system completes all benchmark computations more quickly than either ARM system and is the best choice to minimize time to solution. The ARM64 and ARM32 computational performa...

Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the important design issues is the measurements of the distribution of functional unit usage and the micro operation level parallelism (MLP), which together determine the proper allocation of functional units in the super...

The method used to save and restore the values of registers across function calls can affect performance and influence the design of specific instructions. This paper describes the results of an experiment that empirically evaluated six different schemes for saving and restoring registers on CISC machines. The methods do not require special hardware or interprocedural analysis to be performed. ...

Active learning of register automata infers extended finite state machines (EFSMs) with registers for storing values from a possibly infinite domain, and transition guards that compare data parameters to registers. In this paper, we present RALib, an extension to the LearnLib framework for automata learning. RALib provides an extensible implementation of active learning of register automata, to...