At 60GHz, it becomes difficult to achieve a high power added efficiency (PAE) and large output power for CMOS power amplifier (PA). A parallel class-A and AB pseudo Doherty PA is designed in CMOS 65 nm process to obtain a high PAE and large output power. The PA achieves a 9.8-dB gain at 60GHz. The measured large signal results show that a maximum power added efficiency (PAE) of 14.3% and 12.0% ...

This paper presents the design of a Class A/B power amplifier (PA) for 2.4-2.4835GHz Wireless Sensor Network (WSN) system in 0.18μm CMOS technology. The PA adopts the single-stage differential structure and the output power of the PA can be controlled by switching the sizes of transistors. Seven different level of output power can be obtained through a three-bit control code. The tested results...

Described are the design procedure and measured performance of a PA targeted for the W-CDMA downlink band exhibiting over 84% PAE at 2.14 GHz. The PA is designed with an uncharacterised GaN HEMT. A measurement-based design approach is used to optimise the source and load impedance at the fundamental frequency with classF harmonic terminations enforced. S-parameters extracted from a full-wave EM...

The thermal stability and reliability of AlGaN/GaN high electron mobility transistors (HEMTs) on Si substrates with a 2 μm-thick copper interconnection (Cu-INTC) metal were evaluated. The use of metallic copper as a conducting metal has the advantages of higher thermal conductivity, low cost and low sheet resistance. For comparison, traditional gold metal interconnection (Au-INTC) devices were ...

A novel algorithm for class-A/AB power amplifiers (PA) enhancement is fully described. The principle is to find a combination of base current (gate voltage), collector voltage (drain voltage) and input power for each output power level so that the linearity/efficiency specifications of the application are satisfied. Based on a 1tone static characterization of the amplifier, the algorithm uses a...

There is a lack of educational technology to support cognitive systems engineering topics such as models of human performance in dynamic environments. This paper describes the Cognitive Systems Engineering Educational Software (CSEES) system, an integrated toolset designed to facilitate curricula related to human judgment and decision-making performance modeling and evaluation. CSEES provides s...

A single-stage 24 GHz triple stacked power amplifier using 0.13 μm CMOS process is demonstrated. To Compare with parallel current combining method, series voltage combining method using a stacked amplifier architecture can realize a large output voltage swing from the top transistor without exceeding the transistor breakdown voltage limitations. However, at high frequencies, parasitic capacitan...