In this paper we discussed different switch architectures. We focus mainly on optical buffering. We investigate an all-optical buffer architecture comprising of cascaded stages of quantum-dot semiconductor optical amplifier-based tunable wavelength converters, at 160 Gb/s. We also propose the optical buffer with multi-wavelength converters based on quantum-dot semiconductor optical amplifiers. ...

A cascode CMOS low noise amplifier (LNA) is presented along with the used design methodology and measurement results. The LNA works at 2.4 GHz with 14.5 dB voltage gain and 2.8 dB simulated noise figure (NF). Powered from a 1.8 V supply, the core measured current consumption is 2.76 mA. An output buffer was designed to match a 50 Ω load and its current consumption is 5.5 mA. The technology used...

A 5Gb/s optical receiver front-end for optical interconnection is presented in this paper. A transimpedance amplifier (TIA), limiting amplifiers (LA), output buffer and a bias circuit are integrated in deep Nwell 0.18 m CMOS technology. As the input current amplitude is 30 A, the differential output voltage is achieved to be 124 mV. The linear gain is 78.8dB and consumes 200mW under 1.8V supply...

A switched capacitor circuit which simulates Frequency Dependant Negative Resistor is proposed. The circuit is controlled by three phases clock and needs one unity gain buffer. A comparison among SC FDNRs in other references is shown. SWITCAP simulation of SC filter using these circuits are also shown. Key-Words; Switched-Capacitor(SC) Frequency Dependant Negative Resistor(FDNR) Filter immittan...

Syntax Display A dockable subwindow displays the abstract syntax tree (AST) of the current buffer. This is shown on the left of Fig. 4, where we define the theory from Ex. 2.2 in LF. Here, the green parts are the keywords and separators of our structure parser (see Sect. 4.1). Users can navigate from a buffer position to the respective node in the AST and vice versa, as shown in the jointly sel...

We discuss the design of energy-efficient pipelines for asynchronous VLSI architectures. To maximize throughput in asyn-chronous pipelines it is often necessary to insert buffer stages, increasing the energy overhead. Instead of optimizing pipelines for minimum energy or maximum throughput, we consider a joint energy-time metric of the form ¼ is the energy per operation and ½ is the time per op...

This paper considers VBR transmission of multiple real-time videos over ATM networks. Multiple real-time VBR video sources are multiplexed into an ATM switch to transmit cells into the network. Given the ATM switch capacity, the problem is to dynamically allocate the required channel bandwidth for each video source such that the encoder buffer occupancy is maintained at a target level. To solve...

A modification of the conventional Flipped Voltage Follower (FVF) to enhance its output resistance is presented. It consists of replacing the conventional cascoding transistor of the basic cell by a regulated cascode scheme. This decreases the output resistance by a factor gmro approximately, the gain of a transistor as an amplifying stage. This is achieved with only two additional transistors ...

We discuss the design of energy-efficient pipelines for asynchronous VLSI architectures. To maximize throughput in asynchronous pipelines it is often necessary to insert buffer stages, increasing the energy overhead. Instead of optimizing pipelines for minimum energy or maximum throughput, we consider a joint energy-time metric of the form E , where E is the energy per operation and is the time...