An ADC operation and signal processing scheme in the error measurement mode has been developed to determine error coefficients. A preliminary experiment was performed by using an ADC test circuit to verify the scheme’s effectiveness for precise and dynamic digital calibration. The calibration process was performed by using the evaluated values of error coefficients in the proposed way, and the ...

We show that ferroelectric multilayers are not simple capacitors in series (CIS) and treating these as CIS may lead to misinterpretation of experimental results and to erroneous conclusions. Here, we present a theoretical model of ferroelectric bilayers using basic thermodynamics taking into account the appropriate electrical boundary conditions and electrostatic fields. The spontaneous polariz...

0-89791-851-7$5.00  1997 IEEE 1 Analysis and Design of Multiple-Bit High-Order Modulator Hao-Chiao Hong, Bin-Hong Lin, and Cheng-Wen Wu Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan Abstract|The high-order modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal e ects such as the nite opamp gain and the ca...

This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by stati...

A new phase self-calibrated scheme maintains the quadrature is proposed in the letter, which mainly includes quadrature phase detector (QPD), charge pump, comparator, controller and variable delay buffer (VDB) etc. The primary idea behind the scheme is that the quadrature phase error is converted to the voltage variation on the capacitor, and then the voltage variation drives the controller to ...

A wideband 2-1-1 cascaded ΣΔ modulator with a single-bit quantizer in the two first stages and a 4-bit quantizer in the final stage is developed. To reduce sensitivity of digital-to-analog converter (DAC) nonlinearities in the feedback of the last stage, dynamic element matching (DEM) is introduced. This paper presents two modelling approaches: The first is MATLAB description and the second is ...

This work describes a reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm, 10b low-power 0.13um CMOS two-step pipeline ADC. The SHA employs gate-bootstrapped sampling switches and a two-stage amplifier based on a low-threshold NMOS differential input stage to obtain 10b accuracy even at a 0.5V supply. A signal-isolated all directionally symmetric layout reduces the MDAC capacitor mismatch wh...

The performance of Σ∆ Modulators (Σ∆Ms) is highly dependent of that of their embedded switched-capacitor (SC) network. Therefore, detailed transient models of SC integrators become necessary when modeling Σ∆Ms. This work presents a behavioral transient model of a SC integrator that includes the effects of the amplifier transconductance and output conductance relation; and the dynamic capacitive...

A method for improving the signal-to-noise ratio (SNR) of single-stage sigma-delta modulators (SDMs) with one-bit quantizer is presented. It is well known that uncertainties and noises are sources of error which cause performance degradation. Specifically, the modulators are naturally subject to analog mismatch in capacitor values and finite amplifier gain, which are manifested as parametric un...