Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrie:r effects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design. phase. The electromigration and the hot carier effects are est,imated at the gate level using signal a...

In electromigration degradation process the existing physical defects on interconnect play a critical role by significantly accelerating the EM damage under increased current density and elevated temperature. In this work the simulation models were upgraded in the IC reliability simulator ARET to incorporate the effect of interconnect physical defects in expected lifetime prediction. Then based...

Based on the analysis of operation principles of conventional self-exciting electronic ballast, the cause of high switching loss has been researched. In order to reduce switch temperature and increase the reliability of the whole circuit, drive circuit of self-exciting electronic ballast has been improved to achieve soft switch. Circuit simulations and experimental results are coincided with th...

Negative bias temperature instability has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. In this paper, we construct a comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model. We demonstrate how to solve the reaction–diffusion equations in a way ...

Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies introduce numerous defects so insisting on defectfree crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify rel...

System reliability greatly improved because Push-in terminal block adopted for the power input and Cooling method Diagram of the Input/output circuit block. FET devices, refer to the graph of the backup time to obtain an estimation of the initial value of the stop using it, disconnect the input power supply. Nevertheless, uninterruptible power supply requires a large amount of batteries, discha...

In this paper we address the possibility to improve the reliability of small to middle-size circuits without employing redundancy. Circuits’ reliability is improved by reducing the logic depth of critical paths since the probability of failure of each output of the circuit depends no the logic depth of critical paths. Circuits of the same size were considered, as well as different synthesized v...

In this work a new embedded negative voltage level converter is presented. The proposed circuit converts a positive input signal to a negative output signal obtaining an increased protection by the high voltage stress on the used MOS devices. This results in higher system reliability in applications where negative pulses are required. The circuit has been designed in a 0.18μm triple-well standa...

The ambition constrained validity and the model witness problems in the logic UCL, proposed in [10], for reasoning about circuits with unreliable gates are analyzed. Moreover, two additional problems, motivated by the applications, are studied. One consists of finding bounds on the reliability rate of the gates that ensure that a given circuit has an intended success rate. The other consists of...

Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrier e ects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design phase. The electromigration and the hot carier e ects are estimated at the gate level using signal activi...