This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously proposed QSERL logic, two phase sinusoidal power clocks were used that increased the hardware complexity and clocking issues. In this paper, sin...

Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations. Here, we show that mutually coupled phase-locked loops (PLLs) enable synchronous clocking in large-scale systems with transmission delays. We present a phase descriptio...

Clock disabling for power management has been implemented in some microcontrollers, but the wake-up time of Xtal/PLL-based systems is incompatible with fast interrupt response. On the other hand, hardwired on-chip clocking has been used for dedicated circuits. We illustrate the design issues of a general-purpose microcontroller core with a programmable on-chip fullydigital clock generator. The ...

In this paper, we describe an integer linear programming (ILP) based datapath scheduling algorithm which uses both multiple supply voltages and dynamic frequency clocking for power optimization. The scheduling technique assumes the number and type of different functional units as resource constraints and minimizes the energy delay product (EDP). The energy savings directly comes from the use of...

—A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme causes the starting phase of gated-oscillators to alternate repeatedly between 0° and 1...

We introduce two CAD tools, checkT, and minT, , for timing verification and optimal clocking. Both tools are based on a new timing model of synchronous digital circuits which is: 1) general enough to handle arbitrary multiphase clocking; 2) complete, in the sense that it captures signal propagation along short as well as long paths in the logic; 3) extensible to make it relatively easy to incor...