In this paper, we implement a model of an electric fish, Eigenmannia, that detects frequency differences between the individuals, on analog CMOS circuits. The circuit’s fundamental function is equivalent to a conventional CMOS frequency comparator, although less post-processing is still required. The circuit consists of Pand T-units each of which encodes amplitudes and phases of the monitored e...

A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 μm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The...

A novel circuit model based on a trainable memristorcrossbar network integrated with a CMOS circuit for pattern classification and recognition is proposed and analyzed in this paper. The configurable memristors along each column wires of the crossbar are trained by a standard pattern input from the row wires of the crossbar to represent the pattern. After the training, the crossbar network can ...

We have investigated a chaotic circuit utilizing CMOS ring oscillators[1]. The circuit consists of two CMOS ring oscillators and two diodes. A CMOS ring oscillator is used for CMOS process performance test. This oscillator consists of a series of inverter circuits. It has a very simple structure. Therefore, we consider that the proposed circuit is realized very easily. In the past studies, we h...

This work presents a technique for the onchip generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique consists of a modified low-order analog filter, that provides a sinusoidal output as response to a DC input, combined with a harmonic cancellation strategy to improve the linearity of the generated signal. The propose...

Supply Current Testing (IDDQ) has become an important defect oriented test strategy for digital IC products. The technique takes advantage of the low quiescent supply current drawn by static CMOS circuits relative to the current consumption during state changes. However, in analogue and mixed signal IC’s this condition can rarely be observed, as in most circuits, steady state currents depend on...

This paper presents JPL progress in building evolutionoriented reconfigurable devices. It surveys the FPTA family, and presents details of the latest chip, FPTA2, an array of 64 reconfigurable cells that can implement mixed-signal functions, include programmable capacitors and resistors and integrate photodetectors as part of a built-in vision sensor. The chip was fabricated in 0.18 micron CMOS...

In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and p...