Both test compression tools and ATPGs directly producing compressed test greatly benefit from don’t care values present in the test. Actually, presence of these don’t cares is essential for success of the compression. Contemporary ATPGs produce tests having more than 97% of don’t cares for large industrial circuits, thus high compression ratios can be expected. However, these don’t cares are pl...

&THIS SPECIAL ISSUE represents a snapshot of the progress in test compression, a key strategy for dealing with rapidly growing test data volume. Since the beginning of this decade, test compression has emerged to become an important DFT market segment. Test data volume has grown dramatically with increasing design size and the need for additional tests to target defects in nanometer designs, in...

This paper presents the long data compression and the Cmos transistor count increased new fault technologies theses data compression the large data compression and storing the data are described, for provides high encoding efficiency and scalability with respect to the number of test channels support test channel the support algorithm is Viterbi-based test compression. Instead of using the line...

Test data compression is an effective methodology for reducing test data volume and testing time. In this paper, we present a new test data compression technique based on block merging. The technique capitalizes on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes adva...

In this paper genetic based test data compression is targeted for improving the compression ratio and for reducing the computation time. The genetic algorithm is based on extended pattern run-length coding. The test set contains a large number of X value that can be effectively exploited to improve the test data compression. In this coding method, a reference pattern is set and its compatibilit...

A novel test vector compression/decompression technique is proposed for reducing the amount of test data that must be stored on a tester and transferred to each core when testing a core-based design. A small amount of on-chip circuitry is used to reduce both the test storage and test time required for testing a core-based design. The fully specified test vectors provided by the core vendor are ...