This paper presents a self-calibration circuit to correct the non-monotonic response in the cascading digitally controlled oscillator (DCO). The proposed calibration circuit can solve the non-monotonic problem when the coarse-tuning control code is changed. The proposed DCO implemented with a standard performance 65nm CMOS process can output frequency ranges from 58.7 MHz to 481.6 MHz. And the ...

In this paper; we have reviewed different type of frequency calibration and tuning design, independent from PVT variation. Almost every frequency synthesizer faces these natural process, voltage, and temperature (PVT) variation in modern application design. Generating an accurate frequency reference is desirable, and as it often require, minimum time to achieve optimal tuning frequency and less...

In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 0.964] GHz with [279.429 16.515] μW power consumption variation. VCO designed with five XNO...

Digital RF transceiver architectures increasingly require quadrature (I/Q) local oscillator sinusoid generation, where the phasenoise and power consumption of the quadrature voltage controlled oscillator (QVCO) have a significant impact on the system performance. The relevance of VCO power consumption becomes even more urgent due to the demand for implementations of ultra-low power short-range ...

Barium Strontium Titanate (BST) varactors utilized in a VCO demonstrate unique tuning characteristics compared to junction varactors. A 2.7 GHz microstrip line VCO operates in a tracking phaselock loop configured as an X4 frequency multiplier. BST oscillator tuning and the effect on loop dynamics is observed by the intentional design of an under damped system. Oscillator noise correction and pe...

A frequency synthesizer employing a new digitalfrequency measurement method in a feedback loop is described. The synthesizer features high-frequency resolution and a high operating frequency. The mostly digital nature of the synthesizer and relaxed voltage-controlled oscillator requirements also make the synthesizer suitable for integration. Models for the synthesizer are developed and experime...

| This paper presents a salient method to nd an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. F...

In this paper we present a CMOS quadrature ring oscillator operating at 0.5 V. Due to this very low voltage conditions, new project technique using the available terminal of the transistors (bulk) is used in order to reduce the threshold voltage of the transistors, thus improving the voltage headroom. The technique is applied in a conventional inverter-based ring oscillator with a feedback topo...