Register files (RF) are known to consume about 20% of the power inside a processor. Embedded systems, due to area and timing constraints, generally have small register files, which can cause significant register pressure. This work explores how having a map-table or a map-vector can decrease the power dissipation in the processor. The distribution of register writes and sharing of commonly occu...

A robot-obstacle distance evaluation algorithm is described in this thesis which directly operates on the image given by a depth sensor, also known as Depth Space. The algorithm’s main features are that the entire visible part of the robot is accurately surveyed and that the different robot links are separately considered for the minimum robot-obstacle distance. Several design parameters are de...

The multi-banked register file (MBRF) is an effective approach to reduce the complexity for a monolithic register file. In order to apply the multi-banked register file to a low-power microprocessor, we have to design a dynamic voltage scaling (DVS) approach for the MBRF to reduce its power consumption. However, when the temporary values are stored into an MBRF, their distributed storage locati...

MUMmerGPU uses highly-parallel commodity graphics processing units (GPU) to accelerate the data-intensive computation of aligning next generation DNA sequence data to a reference sequence for use in diverse applications such as disease genotyping and personal genomics. MUMmerGPU 2.0 features a new stackless depth-first-search print kernel and is 13× faster than the serial CPU version of the ali...

In this research, we evaluate NAS Parallel Benchmarks ver.1 Kernel CG on massively parallel processor CP-PACS, and analyze the result. CP-PACS' CPU has a special register which is auto-incremented by clock cycle, and we can instrument time spent for any function routine with very high accuracy. As a result of performance analysis, especially for data transfer time, our desk-top estimation ts to...

Let x t, . . . , X, be variables which together constitute a composite register. These variables are shared by a number of processes which operate in a totally asynchronous and wait-free manner. An operation by a process on the composite register is either a write to one of the variables or a read of the values of all variables. All operations are required to be atomic, i.e. an execution of any...

A novel hardware architecture for memetic vector quantizer (VQ) design is presented in this paper. The architecture uses steady-state genetic algorithm (GA) for global search, and C-means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state GA operations. It also uses a pipeline architecture for the hardware...

We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automatically compares a pipelined implementation to an architectural description. The CPU time needed for veri cation is independent of the data path width, the register le size, and the number of A...

A novel parallel memetic algorithm (MA) architecture for the design of vector quantizers is presented in this paper. The architecture contains a number of modules operating memetic optimization concurrently. Each module uses steady-state genetic algorithm (GA) for global search, and K-means algorithm for local refinement. A shift register based circuit for accelerating mutation and crossover op...

In designing ASIPs (Application Specific Integrated Processors) the papers investigated so far have almost focused on the optimization of the CPU core and did not pay enough attention to the optimization of the RAM and ROM size together. This paper overcomes this limitation and proposes an optimization algorithm to define the best tradeoff between the CPU core, RAM and ROM of an ASIP chip to ac...