In this paper, a unified sequential architecture for 8-point discrete cosine transform and its inverse is described. The architecture is based on rescheduled constant geometry algorithms, which are mapped onto a one-dimensional structure with the aid of vertical projection. The resulting modular architecture can be efficiently pipelined since arithmetic units are removed from the critical path....

One of the problems in future processors will be the resource conflicts caused by several load/store units competing to access the same cache bank. The traditional approach for handling this case is by introducing buffers combined with a cross-bar. This approach suffers from (i) the nondeterministic latency of a load/store and (ii) the extra latency caused by the cross-bar and the buffer manage...

Method for robust schedule preparation for domain of profit based cooperation is introduced in this paper. The method aims schedules, which are prepared and concluded step-by-step during the team formation phase. The method takes into account domain specifics, like incomplete information about the partners, and their various reputation and skill levels. The method is based on critical path disp...

Fast algorithms for high-speed divider design in finite fields GF(2) are very crucial in applications like cryptosystems. In this paper, we reformulated the conventional iterative division algorithm by changing the pre-defined variable and then updating its initial value accordingly. The reformulated division algorithm allows a restructuring of the divider architecture to further improve its op...

Speed of digital arithmetic processor depends mainly on the speed of adders. This paper provides a technique so that we can increase the speed of addition. Hybrid signed digit number representation perform addition in such a way that the carry propagation chain is limited to single digit position and hence are used to speed up arithmetic operation. Also hybrid signed digit reduces the critical ...

Speed of digital arithmetic processor depends mainly on the speed of adders. This paper provides a technique so that we can increase the speed of addition. Hybrid signed digit number representation perform addition in such a way that the carry propagation chain is limited to single digit position and hence are used to speed up arithmetic operation. Also hybrid signed digit reduces the critical ...

Peptide mapping is a widely used technique for the characterization of proteins. This Application Note demonstrates a robust LC method and design space for peptide mapping using a Quality by Design (QbD) approach. A therapeutic monoclonal antibody (mAb) was employed as the model protein in the current peptide mapping study. Fusion QbD software’s multivariate design and analysis capabilities, wh...

We present an architecture for digit-serial multiplication in finite fields GF(2m) with applications to cryptography. The proposed design uses polynomial basis representation and interleaves multiplication steps with degree reduction steps. An M-bit multiplier works with arbitrary irreducible polynomials and can be used for any binary field of order 2m ≤ 2M . We introduce a new method for degre...

We present Parkour, a tool that creates parallel speedup estimates for unparallelized serial programs. Unlike previous approaches, it does not require any prior human analysis or modification of the program. Parkour automatically quantifies the parallelism of a given program and provides an approximate upper bound for performance, modeling fundamental parallelization constraints. For the evalua...

In this paper we introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. Our performance estimate shows that our approach is at least on order of magnitude faster than serial fault emulation used in prior work.