نتایج جستجو برای: dbc

تعداد نتایج: 946  

2013
Jabeom Koo Augusto Tazzoli Jeronimo Segovai-Fernandez Gianluca Piazza Brian P. Otis

A differential Colpitts oscillator using AlN MEMS CMR designed in 0.13 um CMOS is presented in this work. The oscillator operates at 1.16 GHz, with a total power consumption of 4.2 mW at 1 V supply. It achieves a phase noise of -143.6 dBc/Hz, 173.3 dBc/Hz at 100 kHz and 1 MHz offset frequency respectively with a figure of merit (FOM) of 228.3 dB. Current-based temperature compensation was emplo...

2001
Wen-Shiung Chen Shang-Yuan Yuan Hungkuei Hsiao Chih-Ming Hsieh

Two algorithms that can obtain more accurate estimate of the fractal dimension are proposed. One is the shifting DBC (SDBC) algorithm and the other one is the scanning BC (SBC) algorithm. It is theoretically proven that the SDBC algorithm approaches the estimated value closer to the exact fractal dimension than the DBC method. Simulation results show that the proposed algorithms consistently gi...

2011
Mahdi Ebrahimzadeh

78 Abstract— In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -12...

Journal: :SIAM J. Control and Optimization 2013
Mauro Bisiacco Maria Elena Valcher

In this paper two-dimensional (2D) discrete behaviors, defined on the grid Z+ × Z and having the time as (first) independent variable, are investigated. For these behaviors, by emphasizing the causality notion that is naturally associated with the time variable, we introduce two new concepts of controllability. Algebraic characterizations of time-controllability and of zerotime-controllability ...

2004
Yung-Cheng Chang

We compare the frequency detuning properties of optical pulses generated from erbium-doped fiber lasers (EDFL's) by using harmonic mode-locking and regenerative amplification techniques. The frequency detuning range of regeneratively amplified pulse (17.78 kHz) is wider than that of harmonic mode-locked pulses (7 kHz). The regeneratively amplidied EDFL pulse has a smaller pulsewidth (22ps), a h...

Journal: :Pattern Recognition Letters 2010
Baochang Zhang Lei Zhang David Zhang LinLin Shen

This paper introduces the establishment of PolyU near-infrared face database (PolyU-NIRFD) and presents a new coding scheme for face recognition. The PolyU-NIRFD contains images from 350 subjects, each contributing about 100 samples with variations of pose, expression, focus, scale, time, etc. In total, 35,000 samples were collected in the database. The PolyU-NIRFD provides a platform for resea...

2008
Ariel Adam Zinovi Rabinovich Jeffrey S. Rosenschein

We present an extension of the Dynamics Based Control (DBC) paradigm to environment models based on Predictive State Representations (PSRs). We show an approximate greedy version of the DBC for PSR model, EMT-PSR, and demonstrate how this algorithm can be applied to solve several control problems. We then provide some classifications and requirements of PSR environment models that are necessary...

2012
Y. C. Du Z. X. Tang B. Zhang P. Su

A novel K-band harmonic dielectric resonator oscillator (DRO) is presented. Two identical parallel feedback DROs constitute a symmetric structure by sharing the same dielectric resonator (DR). As a result of this special structure, the odd frequency output components offset while the even harmonic frequency components superimposed at the output port. Odd and even mode analysis method is used in...

2014
Jiankang Li Yong-Zhong Xiong Jin He Wen Wu

In this paper, a 42GHz frequency synthesizer fabricated with 0.13μm SiGe BiCMOS technology is presented, which consists of an integer-N fourth-order type-II phase locked loop (PLL) with a LC tank VCO and a frequency doubler. The core PLL has three-stage current mode logic (CML) and five stage true single phase clock (TSPC) logic in the frequency divider. Meanwhile, a novel balanced common-base ...

1999
Chan-Hong Park Beomsup Kim

This paper describes a low-noise, 900-MHz, voltagecontrolled oscillator (VCO) fabricated in a 0.6m CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. Th...

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