The paper presents an application of the VHDL-AMS formalism to the model of a n-MOS transistor named EKV. Our model takes into account several new features specific to deep submicron technology (parasitic resistors and overlap capacitors induced by LDD), and thermalelectronic interactions. We then give some examples of application of this innovative EKV MOS model (inverter, thermal-opto-electro...

A 2D analytical model for the calculation of the subthreshold slope has been derived for deep-submicron Fully-Depleted SO1 MOSFET's using a Green's function solution technique. The accuracy of the equations has been verified by a 2D numerical device simulator. It is shown that the analytically derived model for the subthreshold slope is in good agreement with 2D numerical simulation data.

An efficient parameter extraction strategy suitable for deep submicron CMOS processes is presented. This has been applied to generate a statistical parameter database for a 0.25 micron process and to generate best and worst case models for circuit simulation by means of Principal Component Analysis.

A new Cross-Shared Redundancy (CSR) architecture of embedded memory for yield improvement is proposed. The model of CSR takes into account cluster errors, which are common for deep-submicron technologies. The redundancy scheme is optimized in consideration of low-power and fast operation. A yield model of cross-shared redundancy for the embedded memory is presented.

In deep submicron CMOS and BICMOS technologies, antenna effects affect floating gate charge of usual floating gate test structures, dedicated to capacitor matching measurement. In this paper a new pseudo-floating gate test structure is designed. After test structure and modeling presentation, testing method and results are given for several capacitor layouts (poly-poly and metal-metal). key wor...

Although IDDQ testing has become a widely accepted defect detection technique for CMOS ICs, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, a built-in IDDQ testing circuit is presented, that aims to extend the viability of IDDQ testing in future technologies and first experimental results are discussed.

Quiescent supply current(IDDQ) in deep submicron ICs is derived by circuit simulation and feasibility of IDDQ tests is examined for short defects in ICs fabricated with 0.18μm CMOS process. The results show that IDDQ of each gate depends on input logic values and that shorts can be detected by IDDQ testing if some process variations are small.

An alternative method to fixed quality acceptance limits for in-line yield control is proposed. Our study is based on a sensitivity analysis, which has revealed that conventional parametric yield-control techniques using fixed in-line acceptance (tolerance) limits, as traditionally used in semiconductor manufacturing, are not efficient in deep submicron-size devices.