In this paper, we have proposed a 2D analytical model for Asymmetric gate stack triple metal MOSFET(AGSTMGAAFET) and performed comparative analysis with the simulation results obtained using SILVACO 3D software. Existing devices such as all around single (SMGAAFET), (TMGAAFET), (GSSMGAAFET), (GSTMGAAFET) asymmetric (AGSTMGAAFET) been compared our structure AGSTMGAAFET. Our device provides excel...

The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness tsi wer...

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even 5 nm, has good properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) ~45 mV/V, and switching (ION/IOFF) ~106 shows a higher l...

The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the tra...

We demonstrate Lg = 100 nm high-speed enhancement-mode (E-mode) InAs quantum-well MOSFETs with outstanding high-frequency and logic performance. These devices feature a 3-nm Al2O3 layer grown by atomic layer deposition. The MOSFETs with Lg = 100 nm exhibit VT = 0.2 V (E-mode), RON = 370 Ω · μm, S = 105 mV/dec, DIBL = 100 mV/V, and gm_max = 1720 μS/μm at VDS = 0.5 V. They also have an excellent ...

This paper describes the impression of low-k/high-k dielectric on performance Double Gate Junction less (DG-JL) MOSFET. An analytical model threshold voltage DG-JLFET has been presented. Poisson’s equation is solved using parabolic approximation to find out voltage. The effect high-k various parameters N-type explored. comparative analysis carried between conventional gate oxide, multi oxide an...

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangul...

In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to gate length of 12 nm with Contact poly pitch (CPP) 48 is simulated. NS-TFET investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism P-I-N layout has been incorporated in the nanosheet devices...

The Double Gate FinFET has been designed for 90nm as an alternative solution to bulk devices. The FinFET with independent gate (IDG) structure is designed to control Vth. When the Vth is controlled the leakage current can be decreased by improving its current driving capability. The metal used for the front gate and back gate is TiN. Here the device performance is compared using nitride spacer ...