The operational range of electrostatic MEMS parallel plate actuators can be extended beyond pull-in in the presence of an intermediate dielectric layer, which has a significant effect on the behavior of such actuators. Here, we study the behavior of cantilever beam electrostatic actuators beyond pull-in using a beam model along with a dielectric layer. The results from the simple beam model are...

SiO2/Al2O3 double dielectric stack layer was deposited on the surface of the GaN-based Light-Emitting Diode (LED). The double dielectric stack layer enhances both the electrical characteristics and the optical output power of the LED because the first Al2O3 layer plays a role of effectively passivating the p-GaN surface and the second lower index SiO2 layer increases the critical angle of the l...

The development of high-performance graphene-based nanoelectronics requires the integration of ultrathin and pinhole-free high-k dielectric films with graphene at the wafer scale. Here, we demonstrate that self-assembled monolayers of perylene-3,4,9,10-tetracarboxylic dianhydride (PTCDA) act as effective organic seeding layers for atomic layer deposition (ALD) of HfO(2) and Al(2)O(3) on epitaxi...

Tetracene thin film transistors with rare earth oxide (Nd2O3) as gate dielectric is reported in this work. Rare earth oxide with high dielectric constant and low leakage current improve the performance of the organic thin film transistors (OTFTs). The fabricated tetracene OTFTs have shown good output characteristics with mobility 0.93x10 cm/V.s, ON-OFF ratio 3.3x10, sub-threshold swing 0.06 V/d...

Chemical Mechanical Polishing (CMP) is currently being used in the fabrication of state-of-the-art integrated circuits, and has been identified as an enabling technology for the semiconductor industry in its drive toward gigabit chips and sub-130nm feature sizes. In this project we present the application of a library-based specular spectroscopic scatterometry method, which is capable of gettin...

In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiOxNy) as the pedestal layer and hafnium dioxide layer (HfO2) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of c...

InGaAsP/InP multiple quantum wells with quantum well intermixing (QWI) have been prepared by Impurity-Free Vacancy Disordering (IFVD). The luminescent characteristics were investigated using photoluminescence (PL) and photoreflectance (PR), from which the band gap blueshift was observed. Si3N4, SiO2 and SOG (spin on glass) were used for the dielectric layer to enhance intermixing from the outdi...

A 10-layer stack of bipolar gate dielectric was formed by sequential layer-by-layer deposition using pulsed radio frequency (RF) plasma polymerization of allylamine and vinyl acetic acid monomers. Due to polar groups localized at the interfaces between each consecutive layer by alternating amine (–NH2) and carboxylic acid (–COOH) functional groups, a 60 nm thick multilayer structure demonstrate...

Article history: Available online xxxx a b s t r a c t Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engin...