A novel hybrid number representation is proposed in this paper. It includes the two’s complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of numbe...

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a progra...

Adders are very often in the critical path of a computer, so it is very important that their performance will not limit the cycle time of the machine. In VLSI applications, area and power are also important factors which must be taken into account in the design of a fast adder. One choice is the carry-skip adder, which because of its great topological regularity and layout simplicity is conside...

According to the recently-revived adder model for cell size control, newborn cells of Escherichia coli will grow and divide after having added a constant size or length, 1L, irrespective of their size at birth. Assuming exponential elongation, this implies that large newborns will divide earlier than small ones. The molecular basis for the constant size increment is still unknown. As DNA replic...

We consider the problem of constructing fast and small binary adder circuits. Among widely-used adders, the Kogge-Stone adder is often considered the fastest, because it computes the carry bits for two n-bit numbers (where n is a power of two) with a depth of 2 log2 n logic gates, size 4n log2 n, and all fan-outs bounded by two. Fan-outs of more than two are avoided, because they lead to the in...

A novel hybrid number representation is proposed in this paper. It includes the two's complement representation and the signed-digit mpresentation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number...

VLSI Integer adders find applications in Arithmetic and Logic Units (ALUs), microprocessors and memory addressing units. Speed of the adder often decides the minimum clock cycle time in a microprocessor. The need for a Parallel Prefix Adder (PPA) is that it is primarily fast when compared with a ripple carry adder. PPA is a family of adders derived from the commonly known carry look ahead adder...

we proposed a new adder design, called VariableLatency Adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder, while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of Negative Bias Temperature Instability (NBTI) on circuit delay. By applying VL-adder concept to 64-bit ca...

In this paper, Carry Tree Adders are Proposed. Parallel prefix adders have the best performance in VLSI Design. Parallel prefix adders gives the best performance compared to the Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). Here Delay measurements are done for Kogge-Stone Adder, Sparse Kogge-Stone Adder and Spanning Tree Adder. Speed of Kogge-Stone adder and Sparse Kogge-Stone adder have...