Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting/propagating these target faults. Adding scan to the circuit increases reachability of these hardto-reach and/or previously unreachable states. In this paper, we postulated that fewer scan ipops are needed to make these states reachable. The states necess...

The paper investigates the possibilities of application of random generated test sequences for at-speed testing of non-scan synchronous sequential circuits. Our research shows that relatively long random test sequences exhibit better transition fault coverages than tests produced by deterministic ATPG tools. We proposed an approach for dividing of long test sequences into subsequences. The appl...

The basic methodologies for creating at-speed test patterns are covered in numerous sources.2 While creating at-speed test patterns, it is important to account for timing exceptions and constraints such as false and multicycle paths. If these paths are not handled correctly during scan-based at-speed test pattern generation, it can lead to lower test quality and failing good chips on the tester...

This paper introduces an architecture for aggregation of output from different diagnostic tools. The diagnostic fusion tool deals with conflict resolution where diagnostic tools disagree, temporal information discord where the estimate of different tools is separated in time, differences in information updates where the classifiers are updated at different rates, fault coverage discrepancies, a...

Delay fault testing has proven to be a significant part of modern manufacturing testing. It has also become a source of overtesting due to detection of functionally untestable faults by invalid transitions that would not occur during functional operation of the chip. There has been previous work in the field that identifies these faults allowing them to be removed from active fault lists from A...

Systems constructed from components, including distributed systems, consist of a number of elements that interact with each other. As the number of network elements or interchangeable components for each network element increases, the trade off that the system tester faces is the thoroughness of test configuration coverage, versus availability of limited resources (time and budget). An approach...

In this paper we analyze the situation when the tests are generated for a particular implementation. In this case there rises a question – can a test generated for one implementation be used for another implementation? Naturally, that a test generated according to one structure may not detect all specified faults of another structure. In this work we explore the test quality of one realization ...

This paper introduces the concept of antirandom testing where each test applied is chosen such that its total distance from all previous tests is maximum. This spans the test vector space to the maximum extent possible for a given number of vectors. This strategy results in a higher fault coverage when the number of vectors that are applied is limited. Results on several ISCAS benchmarks show t...

This paper presents a review of existing defect level models and introduces a new defect level model that accounts for the fault clustering effect. The model uses generalized negative binomial statistics to model the probability distribution of the number of faults in a chip. This analysis shows that clustering, in addition to naturally increasing the yield, also raises the detection probabilit...

In this paper, we model the relation between testing e ort, coverage and reliability. We present a logarithmic model that relates testing e ort to test coverage (block, branch, c-use or p-use). The model is based on the hypothesis that the enumerables (like branches or blocks) for any coverage measure have di erent detectability, just like defects have di erent detectability. This model allows ...