Thwarting severe cryptographic hardware attacks requires new approaches to logic and physical designs. This paper presents a systematic design approach to fault tolerant cryptographic hardware designs by combining the concurrent error detection and correction, and uniform switching activity cells. The effectiveness of the Hamming code based error correction schemes as a fault tolerance method i...

A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-tolerant controller structure utilizes the rollback hardware also for system mode and this way achieves performance improvements of more than 50% compared to controller structures made fault tolerant by conventional tech...

A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-tolerant controller structure utilizes the rollback hardware also for system mode and this way achieves performance improvements of more than 50% compared to controller structures made fault tolerant by conventional tech...

For ordinary circuits with a xed upper bound on the maximal fanin of gates it has been shown that logarithmic redundancy is necessary and suucient to overcome random hardware faults. Here, we consider the same question for unbounded fanin circuits that in the noiseless case can compute Boolean functions in sublogarithmic depth. In this case the details of the fault model become more important. ...

The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Volta...

Determining the optimal implementation of a quantum gate is critical for designing a quantum computer. We consider the crucial task of efficiently decomposing a general single-qubit quantum gate into a sequence of fault-tolerant quantum operations. For a given single-qubit circuit, we construct an optimal gate sequence consisting of fault-tolerant Hadamard (H) and π/8 rotations (T ). Our scheme...

The use of trapped atomic ions in the field of quantum information processing is briefly reviewed. We summarize the basic mechanisms required for logic gates and the use of the gates in demonstrating simple algorithms. We discuss the potential of trapped ions to reach fault-tolerant error levels in a large-scale system, and highlight some of the problems that will be faced in achieving this goa...

A quantum circuit is generalized to a nonunitary one whose constituents are nonunitary gates operated by quantum measurement. It is shown that a specific type of one-qubit nonunitary gates, the controlled-not gate, as well as all one-qubit unitary gates constitute a universal set of gates for the nonunitary quantum circuit, without the necessity of introducing ancilla qubits. A reversing measur...