Orthogonal Frequency Division Multiplexing (OFDM) is the most widely used modulation technique for wireless communication network. In this paper, 4 x 4 spatially multiplexed MIMO OFDM transceiver is designed using 1/2 encoder and 64 bit FFT. The implementation has been carried out in hardware using Field Programmable Gate Array (FPGA). Both the transmitter and the receiver are implemented on a ...

Algorithms used in signal processing, image processing and high performance computing applications are computationally intensive. For efficient implementation of such algorithms with efficient utilization of available resources, an indepth knowledge of the targeted field programmable gate array (FPGA) technology is required. This paper presents a state-ofthe-art review of the architectures and ...

This paper presents the hardware implementation of a neural network controller for a nonlinear system. As a learning algorithm for a neural network, the reference compensation technique has been implemented on a low cost micro-controller unit (MCU), while PID controllers with counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate arra...

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The p...

Synchronization is a critical operation required by majority of wireless receivers. This paper presents the design, implementation, and evaluation of an orthogonal frequency-division multiplexing baseband packet synchronizer deployed on a field-programmable gate array (FPGA). Packet detection, carrier frequency offset estimation/correction, and time synchronization are all performed in the time...

A programmable vector processor and its implementation on a Field-Programmable Gate Array (FPGA) board are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 single-precision floating-point standard and also the efficient implementation of some sparse matrix operations. The processor runs at 70 MHz on the ...

Elliptic curve cryptography (ECC) is an alternative to traditional techniques for public key cryptography. It offers a smaller key size without sacrificing security strength. Previous work found that a hardware implementation of ECC has better performance than the software implementation. Since the performance of a typical elliptic curve cryptosystem is based on the execution time of the encryp...

A field programmable gate array (FPGA) semi-systolic implementation of a modular exponentiation unit, suitable for use in implementing the RSA public key cryptosystem is presented. The design is carefully matched with features of the FPGA architecture, utilizing embedded 18×18-bit multipliers on the FPGA and employing a carry save addition scheme. Using this architecture, a 1024-bit modular exp...

A high performance substitution box (S-Box) implementation using reduced residue of prime numbers is presented in this paper. The byte substitution implemented using S-Box is an important part of the Advanced Encryption Standard (AES). The objective of this paper is to present an efficient Field Programmable Gate Array (FPGA) realization of S-Box using very high speed integrated circuit hardwar...

In this paper, we present a configurable FPGA-based hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The proposed pipelined architecture...