Abstract: We present the optimization of the manufacturing process of the 5nm bulk-FinFET technology by using the 3D process and device simulations. In this paper, bysimulating the manufacturing processes, we focus on optimizing the manufacturingprocess to improve the drive current of the 5nm FinFET. The improvement of drivecurrent is one of the most important issues in ...

According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising techno...

As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...

This paper describes the design of a bandgap reference, implemented in 32 nm FinFET technology. The paper introduced new method for increasing stability of output voltage of bandgap circuit. In the proposed architecture extra feedback is used for setting the output voltage in fixed voltage. This feedback makesbandgap circuit more stable and speedy employing back gate biasing of the FinFET devic...

The manufacturing of modern semiconductor devices involves a complex set of nanoscale fabrication processes that are energy and resource intensive. There is a need for a comprehensive analysis of environmental impacts when an innovative new manufacturing approach emerges for semiconductor circuits. FinFET devices, a special kind of quasi-planer double gate devices, have been introduced as the n...