Little research in compiler optimizations has been undertaken to eliminate or diminish the negative influence on performance of the huge reconfiguration latency of the available FPGA platforms. In this paper, we propose an interprocedural optimization that minimizes the number of executed hardware configuration instructions taking into account constraints such as the ”FPGA-area placement confli...

p. 1 Prototyping Framework for Reconfigurable Processors p. 6 An Emulator for Exploring RaPiD Configurable Computing Architectures p. 17 A New Placement Method for Direct Mapping into LUT-Based FPGAs p. 27 fGREP Fast Generic Routing Demand Estimation for Placed FPGA Circuits p. 37 Macrocell Architectures for Product Term Embedded Memory Arrays p. 48 Gigahertz Reconfigurable Computing Using SiGe...

The Rijndael algorithm has been selected as the new Advanced Encryption Standard. Several JBits implementations of this algorithm are described which target the Virtex FPGA family. As illustrated by sample code, JBits provides a concise means of creating structured datapaths. JBits design abstractions include conventional ones (such as hierarchical modules, ports, nets and buses) and ones that ...

A field programmable gate array (FPGA) implementation of a coprocessor which uses the WSAT algorithm to solve Boolean satisfiability problems is presented. The input is a SAT problem description file from which a software program directly generates a problem-specific circuit design which can be downloaded to a Xilinx Virtex FPGA device and executed to find a solution. On an XCV300, problems of ...

A core operation in actual circuits, especially in digital signal processing algorithms, is multiplication. Often, the computational performance of a DSP system is limited by its multiplication performance [Pet95]. The implementation of multiplier modules into FPGAs is crucial in terms of area, speed and pin limitation. In many cases, even small multiplier modules will exceed the capacity of on...

Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs raises a number of questions on the management of the reconfigurable resource which leads to the concept of a reconfigurable operating system. A major aspect of such an operating system is task placement. Online placement methods are required that achieve a high placement qual...

This paper introduces JHDLBits, the integration of two prominent FPGA design tools: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a “sandbox” to explore advanced interactions wi...

FPGAs are a useful and flexible alternative to custom design chips, but can suffer from severe interconnection delay. The 3D-FPGA is an alternative to the two-dimensional architecture that has been proposed to reduce these delay problems [2]. Here we present Spiffy – the first tool specifically designed for the placement and global routing of 3DFPGAs. Spiffy produces some of the best results in...

We have recently proposed a tool set that will aid the design of a dynamically reconfigurable processor through the use of a set of analysis and design tools. As part of the tool set, in this paper we propose a heterogeneous hierarchical routing architecture. Compared to hierarchical and symmetrical FPGA approaches building blocks are of variable size. This results in heterogeneity between grou...

Applications of Metric Embedding to Regular IC Optimization Ph. D. Dissertation Padmini Gopalakrishnan Department of Electrical and Computer Engineering Carnegie Mellon University Prof. Lawrence T. Pileggi, Chair In digital IC design methodologies, the design netlist is typically modeled as a graph or hypergraph, and information about its structure or topology is often used in optimization. Oft...