Lee, Yi-Mu. Breakdown and reliability of CMOS devices with stacked oxide/nitride and oxynitride gate dielectrics prepared by RPECVD. (Under the direction of Professor Gerald Lucovsky) Remote-plasma-enhanced CVD (RPECVD) silicon nitride and silicon oxynitride alloys have been proposed to be the attractive alternatives to replace conventional oxides as the CMOS logic and memory technology node is...

Article history: Available online xxxx a b s t r a c t Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engin...

CHARACTERIZATION OF ULTRATHIN GATE DIELECTRICS AND MULTILAYER CHARGE INJECTION BARRIERS by Edwin M. Dons Since the invention of the first integrated circuit, the semiconductor industry has distinguished itself by a phenomenally rapid pace of improvements in device performance. This trend of ever smaller and faster devices is a result of the ability to exponentially reduce feature sizes of integ...

The continuous demand for improved CMOS transistors necessitate smailer device dimensions. The reduction in chip size into the deep sub-micron dimensions opens up new scientific and engineering challenges. One of the most critical material in developing deep sub-micron MOS transistors is high quality ultrathin (a few nm) gate dielectric film. As the gate dielectric thickness is reduced to below...

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical...

Deposition process for thin insulator used in polysilicon gate dielectric of thin film transistors are optimized. Silane and N2O plasma are used to form SiO2 layers at temperatures below 150 ºC. The deposition conditions as well as system operating parameters such as pressure, temperature, gas flow ratios, total flow rate and plasma power are also studied and their effects are discussed.  The p...

Continual scaling of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-45 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided Ni metal gate (FUSI) has been proven to be a promising solution. Ni FUSI metal gate can signifi...

We analyze a modern-day 65nm MOSFET technology to determine its electrical characteristics and intrinsic ballistic efficiency. Using that information, we then predict the performance of similar devices comprised of different materials, such as high-k gate dielectrics and III-V channel materials. The effects of series resistance are considered. Comparisons are made between the performance of the...

We report here on pentacene based organic field effect transistors (OFETs) with a high-k HfO2 gate oxide. HfO2 layers were prepared by two different methods: anodic oxidation and sol–gel. A comparison of the two processes on the electrical properties of OFETs is given. Ultra thin nanoporous (20 nm) sol–gel deposited oxide films were obtained following an annealing at 450 C. They lead to high mo...

It has been clear for a number of years that increasing transistor gate leakage with device scaling would ultimately necessitate an alternative to traditional SiON dielectrics with polysilicon gates. Material systems providing higher dielectric constants, and therefore allowing physically thicker dielectrics, have been the object of extensive research. Such high-k dielectrics, when combined wit...