نتایج جستجو برای: gate insulator
تعداد نتایج: 59368 فیلتر نتایج به سال:
In the past few decades, gate insulators with a high dielectric constant (high-k dielectric) enabling a physically thick but dielectrically thin insulating layer, have been used to replace traditional SiOx insulator and to ensure continuous downscaling of Si-based transistor technology. However, due to the non-silicon derivative natures of the high-k metal oxides, transport properties in these ...
This paper describes using wide energy gap lattice-matched II-VI layers, such as ZnSeTeZnMgSeTe, serving as a high-k gate dielectric for n-channel enhancement mode InGaAs field effect transistors (FETs). The thrust is to reduce interface states at the channel-gate insulator boundary while providing sufficient barrier height to confine the carriers in the channel created by inversion. In additio...
The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed a...
A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming ...
| The issues in scaling the Complementary Metal Oxide Semiconductor (CMOS) transistors in sub-100 nm regime are reviewed. The non-classical CMOS device technologies such as high-k gate dielectrics, strained silicon channel, Silicon On Insulator, multi-gate transistors, and metal gate electrodes, are discussed in detail. These techniques are expected to scale the CMOS devices to an ultimate limi...
Electron transport in ultrathin double-gate (DG) silicon-on-insulator (SOI) devices is studied as a function of the transverse electric field and the silicon layer thickness, with particular attention to the evaluation of stationary drift velocity and low-field mobility at room temperature. A one-electron Monte Carlo simulator has been used. 2001 Elsevier Science B.V. All rights reserved.
In this study, a three-dimensional “atomistic” circuitdevice coupled simulation approach is advanced to investigate the process-variation and random dopant induced characteristic fluctuations in planar metal-oxidesemiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, ...
نمودار تعداد نتایج جستجو در هر سال
با کلیک روی نمودار نتایج را به سال انتشار فیلتر کنید