Abstract Quantum-dot cellular automata (QCA) is a likely candidate for future low power nano-scale electronic devices. Sequential circuits in QCA attract more attention due to its numerous application in digital industry. On the other hand, configurable devices provide low device cost and efficient utilization of device area. Since the fundamental building block of any sequential logic circuit ...

Abstract An improved design of a sense amplifier-based flip-flop is presented. The new design overcomes the problems of floating nodes, which is a weakness of previously reported solutions. This is achieved by systematic derivation of flip-flop equations and rearranging the resulting network. The resulting flip-flop outperforms earlier published structures, exhibiting TCQ of 190ps when driving ...

The digital hardware implementation of various fuzzy operations furthermore of fuzzy flip-flops has been the subject of intense study and application. The fuzzy D flip-flop derived from fuzzy J-K one is a single input single output unit with sigmoid transfer characteristics in some particular cases, proper to use as neuron in a Fuzzy Neural Networks (FNN). In this paper we propose the hardware ...

Pulse-triggered flip-flops are mainly used to improve speed of operation (pipeline speed), though flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Usually pulse-triggered flip-flops have specific structures and transistor sizes to optimize the system performance. The transistor size, topology, and threshold voltage of the flip-flop make the timi...

The consumption of power has become an important issue in modern VLSI design. Power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. Multi-bit flip-flop is one of the methods for clock power consumption reduction. This project focuses on reduction of power using multi-bit flipflops by clock synchronization. Two single bit flip-flops are synchronized with ...

In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications. Several art of design techniques have been proposed to eliminate large capacitance in the precharge node of the conventional flip-flop, which drives separately by output pull-up, and pull down transistors. Though the pioneer designs which consumes mu...

In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switc...

BACKGROUND Flip-flops are an item of footwear, which are rubber and loosely secured across the dorsal fore-foot. These are popular in warm climates; however are widely criticised for being detrimental to foot health and potentially modifying walking gait. Contemporary alternatives exist including FitFlop, which has a wider strap positioned closer to the ankle and a thicker, ergonomic, multi-den...

In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce ...

System on chip (SOC) design integrates many complex modules in one chip. As number of modules per chip is increasing, number of transistors in a chip increases resulting in increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. Flip-F...