Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET because most of TFETs are assumed to use on SOI substrates. In this p...

We propose and demonstrate the operation of a monolithic field-effect-transistor-amplified magnetic field sensor device, in which a tunnel-magnetoresistive ~TMR! material is incorporated within the gate of a Si metal–oxide–semiconductor–field-effect transistor. A fixed voltage is applied across the TMR layer, which leads charge to build up within the gate. Applying or changing an external magne...

Single-electron transistor with ferromagnetic outer electrodes and nonmagnetic island is studied theoretically. Nonequilibrium electron spin distribution in the island is caused by tunneling current. The dependencies of the magnetoresistance ratio δ on the bias and gate voltages show the dips which are directly related to the induced separation of Fermi levels for electrons with different spins...

The gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology nodes. In particular, the junctionless transistors are scalable with reduced variability avoidance of steep source/drain junction formation by ion implantation. Here dual-gated p-type field effect transistor demons...

This paper projects the enhanced drive current of a ntype electrostatically doped (ED) tunnel field-effect transistor (ED-TFET) based on heterojunction and band-gap engineering via TCAD 2-D device simulations. The homojunction ED-TFET device utilizes the electrostatic doping in order to create the source/drain region on an intrinsic silicon nanowire that also felicitates dynamic re-configurabil...

full adder cell is often placed in the critical path of other circuits. therefore it plays an important role in determining the entire performance of digital system. moreover, portable electronic systems rely on battery and low-power design is another concern. in conclusion it is a vital task to design high-performance and low-power full adder cells. since delay opposes against power consumptio...

A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (10(15)) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off...

In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to gate length of 12 nm with Contact poly pitch (CPP) 48 is simulated. NS-TFET investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism P-I-N layout has been incorporated in the nanosheet devices...