The dc component, which may be caused by different factors in the grid voltage, is one of disturbances that severely affect performance synchronization systems and, therefore, grid-tied power converters. In phase-locked loop (PLL) and frequency-locked (FLL)-based systems, this article focuses on, some solutions to deal with challenge have been proposed literature. One best available adding reje...

Using the nonlinear second-order phase-locked loop (PLL) model the performance of the heterodyne coherent optical phase shift keying (PSK) systems with Costas loop in multichannel environment is considered in this paper for the first time. The shot noise of the corresponding photodiodes and adjacent channel interferences are described through the signal-to-noise ratio (SNR) in the loop bandwidt...

A low power, adaptive bandwidth tracking Phase Locked Loop (PLL) is presented in this paper. Designed PLL operates over a wide frequency range of 250MHz to 1GHz with a fixed multiplication factor of 8. PLL is optimized for 0.2% UI of r.m.s. jitter over the whole frequency range with bandwidth tracking to keep the power consumption minimum. In addition, a multiplier block is used to increase the...

We propose a novel architecture of an oscillatory neural network that consists of phase-locked loop (PLL) circuits. It stores and retrieves complex oscillatory patterns as synchronized states with appropriate phase relations between neurons.

In the case of grid voltage quality problems, traditional phase-locked loop (PLL) is hard to detect accurate frequency and phase during transient response, which will be detrimental synchronous stability grid-connected inverters. This paper proposes a mode switching based ride-through PLL (TRT-PLL), aiming improve phase-locking performance through detection technique switching. The TRT-PLL inco...

A digital decision-directed phase-locked loop (PLL) for use in optical pulse code-division multiple-access (CDMA) systems based on coherent correlation demodulation is proposed. PLL performance is affected by multiuser interference, laser phase noise and optical shot noise. The effect of these sources of interference and noise on PLL performance is evaluated based on a nonlinear model (the Fokk...

2 Digitizer 1GHz clock generation and control 5 2.1 Digitizer clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Reference generation and coarse clock delay control . . . . . . . . . . . . . . . . . . . 6 2.3 Phase locked-loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Digitizer clock fine delay control . . . . . . . . ...

Based on a practical long-distance large-capacity transmission engineering case, the small-signal stability of fractional frequency system (FFTS) with Y-connected modular multi-level converter (Y-MMC) is mainly researched in this paper. Different from previous control strategies Y-MMC, paper establishes decoupling mathematical model and proposes strategies. Then, Y-MMC obtained. Considering exi...

A digital implementation of a new technique that delivers an extremely accurate and stable phase locked loop system (PLL) is presented. The new technique uses competing phase and frequency loops to incorporate an accurate local reference frequency into the phase locked loop structure. Disturbances on the phase loop caused by the digital frequency loop are identified and a method to mitigate the...

The PLL equivalent augmented system incorporated with state feedback is proposed in this paper. The optimal value of filter time constant of loop filter in the phase-locked loop control system and the optimal state feedback gain designed by using linear quadratic regulator approach are derived. This approach allows the PLL control system to employ the large value of the phasefrequency gain d K ...