Abstract The paper presents a split-level sinusoidal power supply clock generator circuit for Two-Phase Adiabatic Static CMOS Logic circuit (2PASCL). The driving of adiabatic logic requires adiabatic controlled sources of voltage. We study the clock voltage generator circuit using SPICE simulation and investigate the most suitable scheme and highest energy efficiency for the energy recovery pow...

Received Dec 9, 2016 Revised Mar 27, 2017 Accepted Jun 11, 2017 The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the para...

A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem ...

Two approaches for a quantum logic circuit simulator based on Quantum Multiple-valued Decision Diagrams (QMDDs) are formulated and compared. The two approaches for quantum logic circuit simulation are performed by explicit multiplication using QMDD representations of the circuit and input vector, and through implicit multiplication where the QMDD representing the circuit undergoes a guided trav...

Defuzzifier circuit is one of the most important parts of fuzzy logic controllers that determine the output accuracy. The Center Of Gravity method (COG) is one of the most accurate methods that so far been presented for defuzzification. In this paper, a simple algorithm is presented to generate triangular output membership functions in the Mamdani method using the multiplier/divider circuit and...

In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 M...

Nowadays reversible circuit designing is the emerging area of research. This design strategy aims towards the formation of digital circuits with ideally zero power dissipation. In this paper we have proposed a new reversible logic module to design a 4-bit binary 2‟s complement circuit. This complement circuit using reversible logic can be used to design other low loss Arithmetic circuit. Propos...

Motivated by improvements in low-temperature polysilicon thin-film transistor (LTPS-TFT) processes, we designed a TFT-based dynamic-logic programmable logic array (PLA). We report the successful operation of the circuit with high repeatability. We thus demonstrate that the LTPS-TFT technology is mature enough to support aggressive circuit techniques such as dynamic logic.

Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive numbe...

The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain ad...